Deep Sleep Mode Clock Gating Control Register 2 (Dcgc2); Deep Sleep Mode Clock Gating Control Register 2 (Dcgc2) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Registers

1.13.7.21 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)

Figure 1-113. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
31
Reserved
R-0
23
15 14
Reserved
R-0
7 6
GPIOH GPIOG
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-124. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Field Descriptions
Bit Field
31-29 Reserved
28 EMAC0
27-17 Reserved
16 USB
15-14 Reserved
13 µDMA
12-9 Reserved
8 GPIOJ
7 GPIOH
6 GPIOG
5 GPIOF
4 GPIOE
3 GPIOD
238
System Control and Interrupts
29 28
EMAC0
R/W-0
Reserved
R-0
13 12
µDMA
R/W-0
5 4
GPIOF GPIOE
Value Description
Reserved
EMAC0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the EMAC0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
USB0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the USB module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
µDMA Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the µDMA module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
GPIOJ Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOJ module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOH Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOH module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOG Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOG module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOF Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOF module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOE Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOE module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
GPIOD Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the GPIOD module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Copyright © 2012–2019, Texas Instruments Incorporated
27
Reserved
R-0
Reserved
R-0
3 2
GPIOD GPIOC
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
24
17 16
9 8
GPIOJ
1 0
GPIOB GPIOA
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