Gpio Open Drain Select (Gpioodr) Register; Gpio Pull-Up Select (Gpiopur) Register; Gpio Open Drain Select (Gpioodr) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.6.11 GPIO Open Drain Select (GPIOODR) Register, offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-
drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the corresponding
bit should also be set in the GPIO Digital Enable (GPIODEN) register. The GPIO acts as an open-drain
input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO
is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until
the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate Function
Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set (see examples in
Section 4.1.4).
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-16. GPIO Open Drain Select (GPIOODR) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 ODE
4.1.6.12 GPIO Pull-Up Select (GPIOPUR) Register, offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on the
corresponding GPIO signal is enabled. Write access to this register is protected with the GPIOCR register.
Bits in GPIOCR that are cleared prevent writes to the equivalent bit in this register.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPUR=0, and GPIOPCTL=0. A Power-On-Reset (POR) or asserting XRS puts the pins
back to their default state.
NOTE: The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7).
Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register, GPIO
Pull Up Select (GPIOPUR) register, GPIO Select Core (GPIOCSEL) register, and GPIO
Digital Enable (GPIODEN) register are not committed to storage unless the GPIO Lock
(GPIOLOCK) register has been unlocked and the appropriate bits of the GPIO Commit
(GPIOCR) register have been set.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
354
General-Purpose Input/Output (GPIO)
Figure 4-14. GPIO Open Drain Select (GPIOODR) Register
R-0
Value Description
Reserved
Output Pad Open Drain Enable
0 The corresponding pin is not configured as open drain.
1 The corresponding pin is configured as open drain.
Figure 4-15. GPIO Pull-Up Select (GPIOPUR) Register
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
Reserved
R-0
8 7
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
ODE
R/W-0
PUE
R/W-0
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