Analog I/O Toggle (Aioset, Aioclear, Aiotoggle) Register; Analog I/O Set (Aioset) Register Field Descriptions; Analog I/O Clear (Aioclear) Register Field Descriptions; Analog I/O Toggle (Aiotoggle) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

C28 General-Purpose Input/Output (GPIO)

4.2.7.34 Analog I/O Toggle (AIOSET, AIOCLEAR, AIOTOGGLE) Register

The Analog I/O Toggle (AIOSET, AIOCLEAR, AIOTOGGLE) register is shown and described in the figure
and table below.
Figure 4-75. Analog I/O Toggle (AIOSET, AIOCLEAR, AIOTOGGLE) Register
31 30
Reserved AIO30
R-0 R/W-x
23 22
Reserved AIO22
R-0 R/W-x
15 14
Reserved AIO14
R-0 R/W-x
7 6
Reserved AIO6
R-0 R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after resetR/W-x
Bits Field
31-0 AIOn
Table 4-92. Analog I/O Clear (AIOCLEAR) Register Field Descriptions
Bits Field
31-0 AIOn
Table 4-93. Analog I/O Toggle (AIOTOGGLE) Register Field Descriptions
Bits Field
31-0 AIOn
422
General-Purpose Input/Output (GPIO)
29 28
Reserved AIO28
R-0 R/W-x
21 20
Reserved AIO20
R-0 R/W-x
13 12
Reserved AIO12
R-0 R/W-x
5 4
Reserved AIO4
R-0 R/W-x
Table 4-91. Analog I/O Set (AIOSET) Register Field Descriptions
Value
Each AIO pin corresponds to one bit in this register.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to high. If the pin is configured as a AIO output
then it will be driven high. If the pin is not configured as a AIO output then the latch is set but the
pin is not driven.
Value
Each AIO pin corresponds to one bit in this register.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to low. If the pin is configured as a AIO output
then it will be driven low. If the pin is not configured as a AIO output then the latch is cleared but
the pin is not driven.
Value
Each AIO pin corresponds to one bit in this register.
0 Writes of 0 are ignored. This register always reads back a 0.
1 Writing a 1 forces the respective output data latch to toggle from its current state. If the pin is
configured as a AIO output then it will be driven in the opposite direction of its current state. If
the pin is not configured as a AIO output then the latch is cleared but the pin is not driven.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
Reserved AIO26
R-0 R/W-x
19 18
Reserved AIO18
R-0 R/W-x
11 10
Reserved AIO10
R-0 R/W-x
3 2
Reserved AIO2
R-0 R/W-x
Description
Description
Description
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25 24
Reserved
R-0
17 16
Reserved
R-0
9 8
Reserved
R-0
1 0
Reserved
R-0
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