Enable/Disable The Digital Loopback Mode; Enable/Disable The Clock Stop Mode; Register Bit Used To Enable/Disable The Digital Loopback Mode; Receive Signals Connected To Transmit Signals In Digital Loopback Mode - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Receiver Configuration

15.8.4 Enable/Disable the Digital Loopback Mode

The DLB bit determines whether the digital loopback mode is on. DLB is described in
Table 15-20. Register Bit Used to Enable/Disable the Digital Loopback Mode
Register Bit
SPCR1 15
15.8.4.1 Digital Loopback Mode
In the digital loopback mode, the receive signals are connected internally through multiplexers to the
corresponding transmit signals, as shown in
a single DSP device; the McBSP receives the data it transmits.
Table 15-21. Receive Signals Connected to Transmit Signals in Digital Loopback Mode
This Receive Signal
MDR (receive data)
MFSR (receive frame synchronization)
MCLKR (receive clock)

15.8.5 Enable/Disable the Clock Stop Mode

The CLKSTP bits determine whether the clock stop mode is on. CLKSTP is described in
Table 15-22. Register Bits Used to Enable/Disable the Clock Stop Mode
Register Bit
SPCR1 12-11
15.8.5.1 Clock Stop Mode
The clock stop mode supports the SPI master-slave protocol. If you do not plan to use the SPI protocol,
you can clear CLKSTP to disable the clock stop mode.
In the clock stop mode, the clock stops at the end of each data transfer. At the beginning of each data
transfer, the clock starts immediately (CLKSTP = 10b) or after a half-cycle delay (CLKSTP = 11b). The
CLKXP bit determines whether the starting edge of the clock on the MCLKX pin is rising or falling. The
CLKRP bit determines whether receive data is sampled on the rising or falling edge of the clock shown on
the MCLKR pin.
Table 15-23 summarizes the impact of CLKSTP, CLKXP, and CLKRP on serial port operation. In the clock
stop mode, the receive clock is tied internally to the transmit clock, and the receive frame-synchronization
signal is tied internally to the transmit frame-synchronization signal.
1080
C28 Multichannel Buffered Serial Port (McBSP)
Name Function
DLB Digital loopback mode
DLB = 0
DLB = 1
Table
Name Function
CLKSTP Clock stop mode
CLKSTP = 0Xb
CLKSTP = 10b
CLKSTP = 11b
Copyright © 2012–2019, Texas Instruments Incorporated
Digital loopback mode is disabled.
Digital loopback mode is enabled.
15-21. This mode allows testing of serial port code with
Is Fed Internally by
This Transmit Signal
MDX (transmit data)
MFSX (transmit frame synchronization)
MCLKX (transmit clock)
Clock stop mode disabled; normal clocking for
non-SPI mode
Clock stop mode enabled, without clock delay
Clock stop mode enabled, with clock delay
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 15-20.
Reset
Type Value
R/W 0
Table 15-22.
Reset
Type Value
R/W 00
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