Flash Read Control Register (Frdcntl); Flash Read Margin Control Register (Fsprd); Flash Read Control Register (Frdcntl) Field Descriptions; Flash Read Margin Control Register (Fsprd) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Flash Registers
5.4.1 Master Subsystem Flash Control Registers
5.4.1.1

Flash Read Control Register (FRDCNTL)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-86. Flash Read Control Register (FRDCNTL) Field Descriptions
Bit Field
31-12 Reserved
11-8 RWAIT
7-0 Reserved
5.4.1.2

Flash Read Margin Control Register (FSPRD)

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-87. Flash Read Margin Control Register (FSPRD) Field Descriptions
Bit Field
31-2 Reserved
1 RM1
0 RM0
512
Internal Memory
Figure 5-82. Flash Read Control Register (FRDCNTL)
Reserved
R-0
Value Description
Reserved
Random read waitstate
These bits indicate how many waitstates are added to a flash read access. The
RWAIT value can be set anywhere from 0 to 0xF. For a flash access, data is
returned in RWAIT+1 M3-SYSCLK cycles.
Note: The required wait states for each SYSCLK frequency can be found in the
device data manual.
Reserved
Figure 5-83. Flash Read Margin Control Register (FSPRD)
Reserved
R-0
Value Description
Reserved
0 Read Margin 1 mode is disabled
1 Read Margin 1 mode is enabled
0 Read Margin 0 mode is disabled
1 Read Margin 0 mode is enabled
Copyright © 2012–2019, Texas Instruments Incorporated
12 11
RWAIT
R/W-0xF
Reserved
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8 7
Reserved
R-0
2 1
RM1 RM0
R/W-0 R/W-0
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