Registers, Offset 0X070 And 0X08C; Epi Fifo Level Selects (Epififolvl) Register, 0X200; Epi Read Fifo (Epireadfifo) Register [Offset 0X070] And Epi Read Fifo Alias; Registers [Offset 0X074 - 0X08C] - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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17.11.17 EPI Read FIFO (EPIREADFIFO) Register and EPI Read FIFO Alias 1-7

(EPIREADFIFO1-7) Registers, offset 0x070 and 0x08C

This register returns the contents of the NBRFIFO or 0 if the NBRFIFO is empty. Each read returns the

data that is at the top of the NBRFIFO, and then empties that value from the NBRFIFO. The alias registers

can be used with the LDMIA instruction for more efficient operation (for up to 8 registers). See Cortex™-

M3 Instruction Set Technical Reference Manual for more information on the LDMIA instruction.

Figure 17-44. EPI Read FIFO (EPIREADFIFO) Register [offset 0x070] and

EPI Read FIFO Alias 1-7 (EPIREADFIFO1-7) Registers [offset 0x074 - 0x08C]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

EPI Read FIFO Alias 1-7 (EPIREADFIFO1-7) Registers Field Descriptions

This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller or,

more efficiently, a DMA request to the μDMA. The NBRFIFO select triggers on fullness such that it triggers

on match or above (more full) in order for the processor or the μDMA to extract the read data. The WFIFO

triggers on emptiness such that it triggers on match or below (less entries) in order for the processor or

the μDMA to insert more write data).

It should be noted that the FIFO triggers are not identical to other such FIFOs in these peripherals. In

particular, empty and full triggers are provided to avoid wait states when using blocking operations.

The settings in this register are only meaningful if the µDMA is active or the interrupt is enabled.

Additionally, this register allows protection against writes stalling and notification of performing blocking

reads which stall for extra time due to preceding writes. The two functions behave in a non-orthogonal way

because read and write are not orthogonal.

The write error bit configures the system such that an attempted write to an already full WFIFO abandons

the write and signals an error interrupt to prevent accidental latencies due to stalling writes.

The read error bit configures the system such that after a read has been stalled due to any preceding

writes in the WFIFO, the error interrupt is generated. Note that the excess stall is not prevented, but an

interrupt is generated after the fact to notify that it has happened.

Figure 17-45. EPI FIFO Level Selects (EPIFIFOLVL) Register [offset 0x200]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUH22I – April 2012 – Revised November 2019

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Table 17-30. EPI Read FIFO (EPIREADFIFO) Register and

This field contains the data that is at the top of the NBRFIFO. After being read, the NBRFIFO entry

External Peripheral Interface (EPI)

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