Interrupt Generation; Receive Interrupt Generation; Receive Interrupt Sources And Signals - Texas Instruments Concerto F28M35 Series Technical Reference Manual

McBSP Registers
Table 15-91. Use of the Transmit Channel Enable Registers (continued)
Number of
Selectable
Channels XCERx
XCERE
XCERF
XCERG
XCERH

15.12.12 Interrupt Generation

McBSP registers can be programmed to receive and transmit data through DRR2/DRR1 and DXR2/DXR1
registers, respectively. The CPU can directly access these registers to move data from memory to these
registers. Interrupt signals will be based on these register pair contents and its related flags.MRINT/MXINT
will generate CPU interrupts for receive and transmit conditions.
15.12.12.1 McBSP Receive Interrupt Generation
In the McBSP module, data receive and error conditions generate two sets of interrupt signals. One set is
used for the CPU and the other set is for DMA.
EOBR condition
McBSP Interrupt Flags
Interrupt
Signal
1144
C28 Multichannel Buffered Serial Port (McBSP)
Block Assignments
Block Assigned
Block 4
Block 5
Block 6
Block 7
Figure 15-80. Receive Interrupt Generation
00
RRDY
01
10
FSR detected
11
RSYNCERR
RINTM bits
Table 15-92. Receive Interrupt Sources and Signals
Interrupt Enables
in SPCR1
RINTM
Bits
Copyright © 2012–2019, Texas Instruments Incorporated
Bit in XCERx
XCE0
XCE1
XCE2
:
XCE15
XCE0
XCE1
XCE2
:
XCE15
XCE0
XCE1
XCE2
:
XCE15
XCE0
XCE1
XCE2
:
XCE15
RINT
RINTENA
Interrupt Enables Type of Interrupt
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Channel Assignments
Channel Assigned
Channel 64
Channel 65
Channel 66
:
Channel 79
Channel 80
Channel 81
Channel 82
:
Channel 95
Channel 96
Channel 97
Channel 98
:
Channel 111
Channel 112
Channel 113
Channel 114
:
Channel 127
MRINT
Interrupt Line
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