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start address and range is dependent on the type of external device and maximum address (as
appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to 0x1 for address
0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to 0x3 for 256 MB. If using
General-Purpose mode and no address at all, program the EPADR field to 0x1 for address
0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field to 0x0 for 256 bytes.
•
To read or write directly, use the mapped address area (configured with the EPIADDRMAP register).
Up to four or five writes can be performed at once without blocking. Each read is blocked until the
value is retrieved.
•
To perform a non-blocking read, see
NOTE: The application should not attempt to access externally until eight system clock cycles after
the EPI has been fully configured.
The following subsections describe the initialization and configuration for each of the modes of operation.
Proper initialization must be done to ensure correct operation. Control of the GPIO states is also
important, as changes may cause the external device to interpret pin states as actions or commands (see
the GPIO chapter, Register Descriptions). Normally, a pull-up or pull-down is needed on the board to at
least control the chip-select or chip-enable as the GPIOs come out of reset in tri-state.
17.6 SDRAM Mode
When activating the SDRAM mode, it is important to consider a few points:
•
Generally, it takes over 100 μs from when the mode is activated to when the first operation is allowed.
The SDRAM controller begins the SDRAM initialization sequence as soon as the mode is selected and
enabled via the EPICFG register. It is important that the GPIOs are properly configured before the
SDRAM mode is enabled, as the EPI controller is relying on the GPIO block's ability to drive the pins
immediately. As part of the initialization sequence, the LOAD MODE REGISTER command is
automatically sent to the SDRAM with a value of 0x27, which sets a CAS latency of 2 and a full page
burst length.
•
The INITSEQ bit in the EPI Status (EPISTAT) register can be checked to determine when the
initialization sequence is complete.
•
When using a frequency range and/or refresh value other than the default value, it is important to
configure the FREQ and RFSH fields in the EPI SDRAM Configuration (EPISDRAMCFG) register
shortly after activating the mode. After the 100-μs startup time, the EPI block must be configured
properly to keep the SDRAM contents stable..
•
The SLEEP bit in the EPISDRAMCFG register may be configured to put the SDRAM into a low-power
self-refreshing state. It is important to note that the SDRAM mode must not be disabled once enabled,
or else the SDRAM is no longer clocked and the contents are lost.
The SIZE field of the EPISDRAMCFG register must be configured correctly based on the amount of
SDRAM in the system.
The FREQ field must be configured according to the value that represents the range being used. Based
on the range selected, the number of external clocks used between certain operations (for example,
PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used, then the only
downside is that the peripheral is slower (uses more cycles for these delays). If a lower frequency is given,
incorrect operation occurs.
See your device-specific data manual's EPI Electricals section for timing details for the SDRAM mode.
SPRUH22I – April 2012 – Revised November 2019
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Section
17.6.4.
Copyright © 2012–2019, Texas Instruments Incorporated
SDRAM Mode
External Peripheral Interface (EPI)
1195
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