C28X Sx Ram Test And Initialization Register 1 (Csxrtestinit1); C28X Sx Ram Test And Initialization Register 1 (Csxrtestinit1) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Table of Contents

Advertisement

RAM Control Module Registers
5.2.3.9

C28x Sx RAM Test and Initialization Register 1 (CSxRTESTINIT1)

Figure 5-49. C28x Sx RAM Test and Initialization Register 1 (CSxRTESTINIT1)
31
15
14
ECCPARTEST
RAMINITS7
S7
R/W-0
R/W-0
7
6
ECCPARTEST
RAMINITS3
S3
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-54. C28x Sx RAM Test and Initialization Register 1 (CSxRTESTINIT1) Field Descriptions
Bit
Field
31-16
Reserved
15
ECCPARTESTS7
14
RAMINITS7
13
ECCPARTESTS6
12
RAMINITS6
11
ECCPARTESTS5
10
RAMINITS5
9
ECCPARTESTS4
474
Internal Memory
13
12
ECCPARTEST
RAMINITS6
S6
R/W-0
R/W-0
5
4
ECCPARTEST
RAMINITS2
S2
R/W-0
R/W-0
Value
Description
Reserved
Enable/Disable RAMTEST Feature for S7 RAM Block if C28X Subsystem is Master for S7 RAM
Block
0
RAMTEST feature is disabled for S7 RAM block.
1
RAMTEST feature is enabled for S7 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization S7. Any reads to this bit will return a 0.
0
No action taken.
1
Initialize all address locations of S7 RAM block with data 0x0 and corresponding data an address
ECC/parity bits. Applicable only if C28x subsystem is master for S7 memory.
Enable/Disable RAMTEST Feature for S6 RAM Block if C28X Subsystem is Master for S6 RAM
Block
0
RAMTEST feature is disabled for S6 RAM block.
1
RAMTEST feature is enabled for S6 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization S6. Any reads to this bit will return a 0.
0
No action taken.
1
Initialize all address locations of S6 RAM block with data 0x0 and corresponding data an address
ECC/parity bits. Applicable only if C28x subsystem is master for S6 memory.
Enable/Disable RAMTEST Feature for S6 RAM Block if C28X Subsystem is Master for S5 RAM
Block
0
RAMTEST feature is disabled for S6 RAM block.
1
RAMTEST feature is enabled for S6 RAM block. ECC/parity logic is bypassed for memory
accesses.
RAM Initialization S6. Any reads to this bit will return a 0.
0
No action taken.
1
Initialize all address locations of S6 RAM block with data 0x0 and corresponding data an address
ECC/parity bits. Applicable only if C28x subsystem is master for S5 memory.
Enable/Disable RAMTEST Feature for S4 RAM Block if C28X Subsystem is Master for S4 RAM
Block
0
RAMTEST feature is disabled for S4 RAM block.
1
RAMTEST feature is enabled for S4 RAM block. ECC/parity logic is bypassed for memory
accesses.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11
10
ECCPARTEST
RAMINITS5
S5
R/W-0
R/W-0
3
2
ECCPARTEST
RAMINITS1
S1
R/W-0
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
9
8
ECCPARTEST
RAMINITS4
S4
R/W-0
R/W-0
1
0
ECCPARTEST
RAMINITS0
S0
R/W-0
R/W-0
Submit Documentation Feedback

Advertisement

Table of Contents
loading

Table of Contents