Gpio Core Select (Gpiocsel) Register; Gpio Core Select (Gpiocsel) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.6.19 GPIO Core Select (GPIOCSEL) Register, offset 0x534
The GPIOCSEL register selects which core controls the pin. If the M3 GPIOs are enabled by the
GPIODEN register, the M3 can still monitor any GPIO, even if it is mapped to the C28 GPIO mux.
NOTE: The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7).
Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register, GPIO
Pull Up Select (GPIOPUR) register, GPIO Core Select (GPIOCSEL) register, and GPIO
Digital Enable (GPIODEN) register are not committed to storage unless the GPIO Lock
(GPIOLOCK) register has been unlocked and the appropriate bits of the GPIO Commit
(GPIOCR) register have been set.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after rese
Table 4-24. GPIO Core Select (GPIOCSEL) Register Field Descriptions
Bit Field
31-8 Reserved
7 CSEL7
6 CSEL6
5 CSEL5
4 CSEL4
3 CSEL3
2 CSEL2
1 CSEL1
0 CSEL0
360
General-Purpose Input/Output (GPIO)
Figure 4-22. GPIO Core Select (GPIOCSEL) Register
R-0
Value Description
Reserved
Core select 7
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 6
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 5
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 4
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 3
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 2
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 1
0 Selects M3 GPIO mux
1 Selects C28 GPIO mux
Core select 0
0 Selects M3 GPIO mux
0 Selects C28 GPIO mux
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7 6 5
CSEL7 CSEL6 CSEL5 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0
R/W-0 R/W-0 R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
4 3 2 1
R/W-0 R/W-0 R/W-0 R/W-0
Submit Documentation Feedback
16
0
R/W-0