Usb Control And Status Endpoint 0 Low Register (Usbcsrl0), Offset 0X102; Usb Control And Status Endpoint 0 Low Register (Usbcsrl0) In Otg A/Host Mode; Usb Control And Status Endpoint 0 Low Register(Usbcsrl0) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

18.5.29 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102

The USB control and status endpoint 0 low 8-bit register (USBCSRL0) provides control and status bits for
endpoint 0.
Mode(s): OTG A or Host
USBCSRL0 in OTG A/Host mode is shown in
Figure 18-34. USB Control and Status Endpoint 0 Low Register (USBCSRL0) in OTG A/Host Mode
7 6
NAKTO STATUS
R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-37. USB Control and Status Endpoint 0 Low Register(USBCSRL0)
Bit Field Value
7 NAKTO
0
1
6 STATUS
0
1
5 REQPKT
0
1
4 ERROR
0
1
3 SETUP
0
1
2 STALLED
0
1
1 TXRDY
0
1
0 RXRDY
0
1
USBCSRL0 in OTG B/Device mode is shown in
1334
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-34
5 4
REQPKT ERROR
R/W-0 R/W-0
in OTG A/Host Mode Field Descriptions
Description
NAK Timeout. Software must clear this bit to allow the endpoint to continue.
No timeout
Indicates that endpoint 0 is halted following the receipt of NAK responses for longer than the time set by
the USBNAKLMT register.
Status Packet. Setting this bit ensures that the DT bit is set in the USBCSRH0 register so that a DATA1
packet is used for the STATUS stage transaction.
No transaction
Initiates a STATUS stage transaction. This bit must be set at the same time as the TXRDY or REQPKT
bit is set.
This bit is automatically cleared when the STATUS stage is over.
Request Packet. This bit is cleared when the RXRDY bit is set.
No request
Requests an IN transaction.
Error. Software must clear this bit.
No error
Three attempts have been made to perform a transaction with no response from the peripheral. The
EP0 bit in the USBTXIS register is also set in this situation.
Setup Packet. Setting this bit always clears the DT bit in the USBCSRH0 register to send a DATA0
packet.
Sends an OUT token.
Sends a SETUP token instead of an OUT token for the transaction. This bit should be set at the same
time as the TXRDY bit is set.
Endpoint Stalled. Software must clear this bit.
No handshake has been received.
A STALL handshake has been received.
Transmit Packet Ready. If both the TXRDY and SETUP bits are set, a setup packet is sent. If just
TXRDY is set, an OUT packet is sent.
No transmit packet is ready.
Software sets this bit after loading a data packet into the TX FIFO. The EP0 bit in the USBTXIS register
is also set in this situation.
Receive Packet Ready. Software must clear this bit after the packet has been read from the FIFO to
acknowledge that the data has been read from the FIFO.
No receive packet has been received.
Indicates that a data packet has been received in the RX FIFO. The EP0 bit in the USBTXIS register is
also set in this situation.
Copyright © 2012–2019, Texas Instruments Incorporated
and described in
3 2
SETUP STALLED
R/W-0 R/W-0
Figure 18-35 and described in
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 18-37.
1 0
TXRDY RXRDY
R/W-0 R/W-0
Table 18-38.
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