Compare B High-Resolution Register (Cmpbhr); Compare B High-Resolution Mirror Register (Cmpbhrm); Counter-Compare D Register (Cmpd) Field Descriptions; Compare B High-Resolution Register (Cmpbhr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Registers
Table 7-46. Counter-Compare D Register (CMPD) Field Descriptions
Bit Field Description
15-0 CMPD The value in the active CMPD register is continuously compared to the time-base counter (TBCTR). When the
values are equal, the counter-compare module generates a "time-base counter equal to counter compare D"
event.
Shadowing of this register is enabled and disabled by the CMPCTL2[SHDWDMODE] bit. By default this
register is shadowed.
• If CMPCTL2[SHDWDMODE] = 0, then the shadow is enabled and any write or read will automatically go to
• If CMPCTL2[SHDWDMODE] = 1, then the shadow register is disabled and any write or read will go directly
• In either mode, the active and shadow registers share the same memory map address.
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-47. Compare B High-Resolution Register (CMPBHR) Field Descriptions
Bit Field
15-8 CMPBHR
7-0 Reserved
Figure 7-98. Compare B High-Resolution Mirror Register (CMPBHRM)
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-48. Compare B High-Resolution Mirror Register (CMPBHRM) Field Descriptions
Bit Field
15-8 CMPBHR
7-0 Reserved
748
C28 Enhanced Pulse Width Modulator (ePWM) Module
the shadow register. In this case, the CMPCTL2[LOADDMODE] bit field determines which event will load
the active register from the shadow register:
to the active register, that is the register actively controlling the hardware.
Figure 7-97. Compare B High-Resolution Register (CMPBHR)
Value Description
00-FFh Compare B High-Resolution Bits
These 8-bits contain the high-resolution portion (least significant 8-bits) of the counter-compare B
value. CMPB:CMPBHR can be accessed in a single 32-bit read/write.
Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPA
register.
Reserved for TI test.
Value Description
00-FFh Compare B High-Resolution Bits
Writes to both the CMPBHR and CMPBHRM locations access the high-resolution (least significant
8-bit) portion of the Counter Compare B value. The only difference is that unlike CMPBHR, reads
from the mirror register, CMPBHRM, are indeterminate (reserved for TI Test).
By default writes to this register are shadowed. Shadowing is enabled and disabled by the
CMPCTL[SHDWBMODE] bit as described for the CMPBM register.
Reserved for TI test.
Copyright © 2012–2019, Texas Instruments Incorporated
CMPBHR
R/W-0
Reserved
R-0
CMPBHR
R/W-0
Reserved
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
8
0
8
0
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