Download Print this page

Texas Instruments TMS320F28004x Technical Reference Manual

Piccolo microcontrollers

page of 2254

/ 2254
Contents
Table of Contents
Bookmarks

Table of Contents

Advertisement

Quick Links

Download this manual

TMS320F28004x Piccolo Microcontrollers

Technical Reference Manual

Literature Number: SPRUI33

November 4 2015 – Revised January 2017

Table of Contents

Advertisement

Chapters

Table of Contents

Need help?

Need help?

Do you have a question about the TMS320F28004x and is the answer not in the manual?

Questions and answers

Pragati Appasaheb Asude

April 23, 2025

I want SPI ordering part Number

User image 68088ff30dc08

0

Summary of Contents for Texas Instruments TMS320F28004x

Page 1 TMS320F28004x Piccolo Microcontrollers Technical Reference Manual Literature Number: SPRUI33 November 4 2015 – Revised January 2017...
Page 2: Table Of Contents
Watchdog Timer ................. 2.9.1 Servicing the Watchdog Timer ..................2.9.2 Minimum Window Check ............... 2.9.3 Watchdog Reset or Watchdog Interrupt Mode Contents SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 3 3.6.7 Boot Modes ..................3.6.8 Boot Data Stream Structure ....................3.6.9 GPIO Assignments ....................3.6.10 DCSM Usage ....................3.6.11 Clock Initialization SPRUI33 – November 4 2015 – Revised January 2017 Contents Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 4 GPIO and Peripheral Muxing ................Internal Pull-up Configuration Requirements ........................Registers ..................6.7.1 GPIO Base Addresses ......................Crossbar (X-BAR) ......................GPIO Input X-BAR Contents SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 5 10.4.1 Analog to Digital Base Addresses 1195 ................. Programmable Gain Amplifier (PGA) 1342 ..............11.1 Programmable Gain Amplifier (PGA) Overview 1343 SPRUI33 – November 4 2015 – Revised January 2017 Contents Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 6 14.1.2 Block Diagram 1408 ....................14.2 Configuring Device Pins 1413 ......................14.3 Input Control Unit 1413 ....................14.4 Primary (Data) Filter Unit 1414 Contents SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 7 1719 .............. 16.3.1 Scale Factor Optimizer Function - int SFO() 1719 ....................16.3.2 Software Usage 1720 ....................Enhanced Capture (eCAP) 1722 SPRUI33 – November 4 2015 – Revised January 2017 Contents Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 8 19.5.2 Position Counter Latch 1792 ................19.5.3 Position Counter Initialization 1794 ................19.5.4 eQEP Position-compare Unit 1795 ....................19.6 eQEP Edge Capture Unit 1796 Contents SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 9 21.8.3 Wake-UP Temporary (WUT) Flag 1885 ................... 21.8.4 Receiver Operation 1885 ..................21.9 Address-Bit Multiprocessor Mode 1885 ..................21.9.1 Sending an Address 1885 SPRUI33 – November 4 2015 – Revised January 2017 Contents Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 10 Controller Area Network (CAN) 1990 ........................24.1 Overview 1991 ....................... 24.1.1 Features 1991 ..................24.1.2 Functional Description 1991 ....................24.1.3 Block Diagram 1992 Contents SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 11 25.1 Introduction and Features 2076 ....................25.1.1 LIN Features 2076 ....................25.1.2 Block Diagram 2077 ..................25.2 LIN Communication Formats 2079 SPRUI33 – November 4 2015 – Revised January 2017 Contents Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 12 26.4.2 Register Protection 2192 ....................26.4.3 Emulation Mode 2192 ......................... 26.5 Registers 2193 ..............26.5.1 Fast Serial Interface Base Addresses 2193 Contents SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 13 2-43. CLKSRCCTL2 Register ....................2-44. CLKSRCCTL3 Register ....................2-45. SYSPLLCTL1 Register ....................2-46. SYSPLLMULT Register ....................2-47. SYSPLLSTS Register SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 14 2-92. DCCVALID0 Register ....................... 2-93. DCCCNT1 Register ....................2-94. DCCCLKSRC1 Register ....................2-95. DCCCLKSRC0 Register ..................2-96. B0_Z1_LINKPOINTER Register List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 15 2-141. REVID Register ....................... 2-142. FUSEERR Register ....................2-143. SOFTPRES0 Register ....................2-144. SOFTPRES2 Register ....................2-145. SOFTPRES3 Register SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 16 2-190. FADDR_TEST Register ....................2-191. FECC_TEST Register ....................2-192. FECC_CTRL Register ....................2-193. FOUTH_TEST Register ....................2-194. FOUTL_TEST Register List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 17 2-239. CEINTSET Register ......................2-240. CEINTEN Register ......................2-241. NMICFG Register ......................2-242. NMIFLG Register ....................2-243. NMIFLGCLR Register SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 18 2-288. CLB4_AC Register ..................2-289. CLA1PROMCRC_AC Register ......................2-290. SPIA_AC Register ......................2-291. SPIB_AC Register ....................2-292. PMBUS_A_AC Register List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 19 2-337. XINT5CR Register ...................... 2-338. XINT1CTR Register ...................... 2-339. XINT2CTR Register ...................... 2-340. XINT3CTR Register ......................3-1. Device Boot Flow SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 20 4-29. _MPC Register ......................4-30. _MAR0 Register ......................4-31. _MAR1 Register ......................4-32. _MSTF Register ......................4-33. _MR0 Register List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 21 6-26. GPBMUX2 Register ......................6-27. GPBDIR Register ......................6-28. GPBPUD Register ......................6-29. GPBINV Register ......................6-30. GPBODR Register SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 22 7-21. INPUTSELECTLOCK Register ..................... 7-22. XBARFLG1 Register ..................... 7-23. XBARFLG2 Register ..................... 7-24. XBARFLG3 Register ..................... 7-25. XBARFLG4 Register List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 23 7-71. OUTPUT8MUX16TO31CFG Register 1051 ..................7-72. OUTPUT1MUXENABLE Register 1054 ..................7-73. OUTPUT2MUXENABLE Register 1058 ..................7-74. OUTPUT3MUXENABLE Register 1062 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 24 Analog Subsystem Block Diagram (64-Pin PM LQFP) 1148 ............9-3. Analog Subsystem Block Diagram (56-Pin RSH VQFN) 1149 .................... 9-4. Analog Group Connections 1150 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 25 10-36. ADCSOC3CTL Register 1243 ....................10-37. ADCSOC4CTL Register 1246 ....................10-38. ADCSOC5CTL Register 1249 ....................10-39. ADCSOC6CTL Register 1252 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 26 10-85. ADCRESULT4 Register 1326 ....................10-86. ADCRESULT5 Register 1327 ....................10-87. ADCRESULT6 Register 1328 ....................10-88. ADCRESULT7 Register 1329 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 27 13-10. COMPSTS Register 1384 ....................13-11. COMPSTSCLR Register 1385 ....................13-12. COMPDACCTL Register 1386 ....................13-13. DACHVALS Register 1388 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 28 14-31. SDCPARM2 Register 1451 ..................... 14-32. SDDATA2 Register 1452 ....................14-33. SDDATFIFO2 Register 1453 ....................14-34. SDCDATA2 Register 1454 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 29 15-18. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization ........................Event 1508 .................... 15-19. Action-Qualifier Submodule 1509 ..............15-20. Action-Qualifier Submodule Inputs and Outputs 1510 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 30 1560 PWM2 PWM1) ............15-64. Control of Two Half-H Bridge Stages (F = N x F 1561 PWM2 PWM1 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 31 15-110. TBPRD Register 1626 ......................15-111. CMPA Register 1627 ......................15-112. CMPB Register 1628 ......................15-113. CMPC Register 1629 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 32 1700 ....................16-5. HRPWM Block Diagram 1701 ............16-6. Required PWM Waveform for a Requested Duty = 40.5% 1703 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 33 18-10. HRSYSCLKCAP Register 1778 ....................18-11. HRCLKCTR Register 1779 ....................18-12. HRCLKCAP Register 1780 ....................19-1. Optical Encoder Disk 1782 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 34 19-47. QCTMRLAT Register 1835 ....................19-48. QCPRDLAT Register 1836 ......................19-49. REV Register 1837 .................... 19-50. QEPSTROBESEL Register 1838 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 35 21-20. SCIFFTX Register 1906 ...................... 21-21. SCIFFRX Register 1908 ....................... 21-22. SCIFFCT Register 1910 ......................21-23. SCIPRI Register 1911 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 36 23-18. Write Byte and Write Word Messages with and without PEC 1963 ............. 23-19. Read Byte and Read Word Messages with and without PEC 1964 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 37 24-23. CAN_TEST Register 2032 ....................24-24. CAN_PERR Register 2033 ....................24-25. CAN_RAM_INIT Register 2034 ..................24-26. CAN_GLB_INT_EN Register 2035 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 38 25-15. ID Reception, Filtering and Validation 2094 ......................25-16. Receive Buffers 2095 ......................25-17. Transmit Buffers 2096 ....................25-18. General Interrupt Scheme 2097 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 39 26-14. RX_FRAME_TAG_UDATA Register 2199 ....................26-15. RX_DMA_CTRL Register 2200 ....................26-16. RX_EVT_STS Register 2201 ....................26-17. RX_CRC_INFO Register 2204 SPRUI33 – November 4 2015 – Revised January 2017 List of Figures Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 40 26-57. TX_USER_CRC Register 2250 ....................26-58. TX_ECC_DATA Register 2251 ....................26-59. TX_ECC_VAL Register 2252 ....................26-60. TX_BUF_BASE Register 2253 List of Figures SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 41 2-41. CLKSRCCTL1 Register Field Descriptions ................2-42. CLKSRCCTL2 Register Field Descriptions ................2-43. CLKSRCCTL3 Register Field Descriptions ................2-44. SYSPLLCTL1 Register Field Descriptions SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 42 2-90. DCCGCTRL Register Field Descriptions .................. 2-91. DCCREV Register Field Descriptions ................. 2-92. DCCCNTSEED0 Register Field Descriptions ............... 2-93. DCCVALIDSEED0 Register Field Descriptions List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 43 2-139. DCSM_BANK1_Z2_REGS Registers ..............2-140. DCSM_BANK1_Z2_REGS Access Type Codes ..............2-141. B1_Z2_LINKPOINTER Register Field Descriptions ............2-142. B1_Z2_LINKPOINTERERR Register Field Descriptions SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 44 2-188. DMACHSRCSEL2 Register Field Descriptions ..................2-189. FLASH_CTRL_REGS Registers ................2-190. FLASH_CTRL_REGS Access Type Codes ................. 2-191. FRDCNTL Register Field Descriptions List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 45 2-237. LSxINITDONE Register Field Descriptions ................. 2-238. GSxLOCK Register Field Descriptions ................2-239. GSxCOMMIT Register Field Descriptions ................. 2-240. GSxACCPROT0 Register Field Descriptions SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 46 2-286. CMPSS3_AC Register Field Descriptions ................2-287. CMPSS4_AC Register Field Descriptions ................2-288. CMPSS5_AC Register Field Descriptions ................2-289. CMPSS6_AC Register Field Descriptions List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 47 2-335. PIECTRL Register Field Descriptions ................... 2-336. PIEACK Register Field Descriptions ................... 2-337. PIEIER1 Register Field Descriptions ................... 2-338. PIEIFR1 Register Field Descriptions SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 48 ROM Memory ....................3-2. Boot ROM Philosophy ..................... 3-3. Device Default Boot Modes ....................3-4. All Available Boot Modes List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 49 Addressing Modes ...................... 4-9. Shift Field Encoding ......................4-10. Operand Encoding ....................4-11. Condition Field Encoding ...................... 4-12. General Instructions SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 50 4-58. _MSTF Register Field Descriptions ..................4-59. _MR0 Register Field Descriptions ..................4-60. _MR1 Register Field Descriptions ..................4-61. _MR2 Register Field Descriptions List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 51 6-26. GPALOCK Register Field Descriptions ..................6-27. GPACR Register Field Descriptions ................6-28. GPBCTRL Register Field Descriptions ................6-29. GPBQSEL1 Register Field Descriptions SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 52 7-13. INPUT7SELECT Register Field Descriptions ................. 7-14. INPUT8SELECT Register Field Descriptions ................. 7-15. INPUT9SELECT Register Field Descriptions ................ 7-16. INPUT10SELECT Register Field Descriptions List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 53 7-63. OUTPUT_XBAR_REGS Access Type Codes 1004 ............7-64. OUTPUT1MUX0TO15CFG Register Field Descriptions 1006 ............7-65. OUTPUT1MUX16TO31CFG Register Field Descriptions 1009 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 54 8-19. SRC_TRANSFER_STEP Register Field Descriptions 1129 .............. 8-20. DST_TRANSFER_STEP Register Field Descriptions 1130 ..............8-21. SRC_WRAP_SIZE Register Field Descriptions 1131 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 55 10-19. ADCINTSEL3N4 Register Field Descriptions 1210 ..............10-20. ADCSOCPRICTL Register Field Descriptions 1212 ..............10-21. ADCINTSOCSEL1 Register Field Descriptions 1215 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 56 10-68. ADCPPB4CONFIG Register Field Descriptions 1312 ..............10-69. ADCPPB4STAMP Register Field Descriptions 1314 ..............10-70. ADCPPB4OFFCAL Register Field Descriptions 1315 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 57 12-9. DACOUTEN Register Field Descriptions 1368 ................12-10. DACLOCK Register Field Descriptions 1369 ................12-11. DACTRIM Register Field Descriptions 1370 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 58 14-23. SDDATA1 Register Field Descriptions 1440 ................14-24. SDDATFIFO1 Register Field Descriptions 1441 ................14-25. SDCDATA1 Register Field Descriptions 1442 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 59 15-9. Additional Dead-Band Operating Modes 1526 ......... 15-10. Dead-Band Delay Values in μS as a Function of DBFED and DBRED 1528 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 60 15-57. TZDCSEL Register Field Descriptions 1634 ................... 15-58. TZCTL Register Field Descriptions 1636 .................. 15-59. TZCTL2 Register Field Descriptions 1638 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 61 .................... 17-2. eCAP Base Address Table 1746 ....................17-3. ECAP_REGS Registers 1747 ................... 17-4. ECAP_REGS Access Type Codes 1747 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 62 19-20. QPOSCTL Register Field Descriptions 1823 ................... 19-21. QEINT Register Field Descriptions 1824 ..................19-22. QFLG Register Field Descriptions 1826 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 63 21-17. SCIFFTX Register Field Descriptions 1906 ................21-18. SCIFFRX Register Field Descriptions 1908 ................21-19. SCIFFCT Register Field Descriptions 1910 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 64 24-4. Programmable Ranges Required by CAN Protocol 2008 ................... 24-5. Message Object Field Descriptions 2018 ................. 24-6. Message RAM Addressing in Debug Mode 2020 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 65 25-4. Timeout Values in T Units 2090 ....................... 25-5. SCI/LIN Interrupts 2098 ....................25-6. I2C Base Address Table 2105 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 66 26-16. RX_FRAME_TAG_UDATA Register Field Descriptions 2199 ................ 26-17. RX_DMA_CTRL Register Field Descriptions 2200 ................26-18. RX_EVT_STS Register Field Descriptions 2201 List of Tables SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 67 26-62. TX_ECC_DATA Register Field Descriptions 2251 ................26-63. TX_ECC_VAL Register Field Descriptions 2252 ................. 26-64. TX_BUF_BASE Register Field Descriptions 2253 SPRUI33 – November 4 2015 – Revised January 2017 List of Tables Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 68: Preface
For a complete listing of related documentation and development-support tools for these devices, visit the Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set Reference Guide (SPRU430) and TMS320C28x Floating Point Unit and Instruction Set Reference Guide (SPRUEO2) must be used in conjunction with this TRM.
Page 69: C28X Processor
This chapter contains a modified description of the C28x Processor and provides links to access their respective references guides..........................Topic Page ......................Overview SPRUI33 – November 4 2015 – Revised January 2017 C28x Processor Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 70: Overview
= sin(b*2pi) COSPUF32 RaH,RbH a = cos(b*2pi) ATANPUF32 RaH,RbH a = atan(b)/2pi QUADF32 RaH,RbH,RcH,RdH Operation to assist in calculating ATANPU2 C28x Processor SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 71: Viterbi, Complex Math And Crc Unit (Vcu)
C28x plus VCU and C28x+VCU both refer to the C28x CPU with enhancements to support viterbi decode, complex math and CRC. SPRUI33 – November 4 2015 – Revised January 2017 C28x Processor Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 72 Overview www.ti.com • Some devices have both the FPU and the VCU. These are referred to as C28x+FPU+VCU. C28x Processor SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 73: System Control
2.11 Memory Controller Module ..................2.12 Flash and OTP Memory ..............2.13 Dual Code Security Module (DCSM) ......................2.14 Registers SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 74: Introduction
Power Management 2.2.1 Internal 1.2-V Switching Regulator (DC-DC) The internal DC-DC regulator is disabled by default. To use this supply, the TMS320F28004x MCU core must power up initially with the internal LDO (VREG) and then transition to the internal DC-DC regulator via application software.
Page 75: Device Identification And Configuration Registers
XRS. This pin may be used to drive reset pins for other ICs in the application, and may itself be driven by an external source. The XRS is driven internally during watchdog, NMI, and power-on resets. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 76: Power-On Reset (Por)
(SCCRESET) is similar to a SYSRS. However, the security reset also resets the debug logic to deny access to a potential attacker. After a security reset, the SCCRESETn bit in RESC is set. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 77: Peripheral Interrupts
Often, the bits in the status register must be cleared manually before another interrupt will be generated. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 78: Interrupt Entry Sequence
4. The interrupt is latched in IFR.x. 5. If IER.x is set, the interrupt propagates. 6. If INTM is clear, the CPU receives the interrupt. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 79: Configuring And Using Interrupts
To disable all interrupts, set the CPU's global interrupt mask via DINT or SETC INTM. It is not necessary to add NOPs after setting INTM or modifying IER – the next instruction will execute with interrupts disabled. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 80 PWMs. If the PIEVERRADDR register value has not been set, the default boot ROM handler at address 0x003FFFBE is used. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 81: Pie Channel Mapping
CLA OVER FLOW UNDER RECTABLE RRECTABL SS_VIOLAT SLIP FLOW UNDER FLOW _ERROR E_ERROR FLOW Note: Cells marked "-" are Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 82: Vector Tables
User-Defined Trap USER 10 0x0000 0D3A User-Defined Trap USER 11 0x0000 0D3C User-Defined Trap USER 12 0x0000 0D3E User-Defined Trap System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 83: Pie Interrupt Vectors
INT3.2 0x0000 0D62 EPWM2 interrupt INT3.3 0x0000 0D64 EPWM3 interrupt INT3.4 0x0000 0D66 EPWM4 interrupt INT3.5 0x0000 0D68 EPWM5 interrupt SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 84 SDFM1 interrupt INT5.10 0x0000 0E42 Reserved INT5.11 0x0000 0E44 Reserved INT5.12 0x0000 0E46 Reserved INT5.13 0x0000 0E48 SDFM1 DR interrupt 1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 85 FSITX_INT2 INT7.13 0x0000 0E68 FSIRX_INT1 INT7.14 0x0000 0E6A FSIRX_INT2 INT7.15 0x0000 0E6C CLAPROMCRC interrupt INT7.16 0x0000 0E6E Reserved 16 (Lowest) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 86 0x0000 0DD4 ADCA3 interrupt INT10.4 0x0000 0DD6 ADCA4 interrupt INT10.5 0x0000 0DD8 ADCB event interrupt INT10.6 0x0000 0DDA ADCB2 interrupt System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 87 Flash correctable error interrupt INT12.12 0x0000 0EB6 RAM access violation interrupt INT12.13 0x0000 0EB8 PLL slip interrupt INT12.14 0x0000 0EBA Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 88 Description Core priority ePIE group Priority INT12.15 0x0000 0EBC CLA overflow interrupt INT12.16 0x0000 0EBE CLA underflow 16 (Lowest) interrupt System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 89: Exceptions And Non-Maskable Interrupts
Since the SWERR flag is never set by a real hardware fail, it can be used to implement a self-test mode for the NMI subsystem. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 90: Illegal Instruction Trap (Itrap)
All GPIO pins are inputs on power-up. If the state of the chosen ERRORSTS pin during power-up is important, an external pull-up should be connected to the pin. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 91: Clocking
NF = IMULT + FMULT/4 2.7.1 Clock Sources All of the clocks in the device are derived from one of four clock sources. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 92: Using Gpio18 When Intosc2 Is The Sysclk Source
A single-ended 3.3V external clock. The clock signal should be connected to X1, as shown in Figure 2- 6. X2/GPIO18 is not available as a GPIO. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 93: Single-Ended 3.3V External Clock
An external resonator. The resonator should be connected across X1 and X2 with its ground connected to VSS as shown in Figure 2-8. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 94: Derived Clocks
(M0 and M1), and the boot ROM and flash wrapper. This clock is identical to PLLSYSCLK, but is gated when the CPU enters IDLE, STANDBY, or HALT mode. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 95: Xclkout
Table 2-6. Clock Connections Sorted by Clock Domain Clock Domain Module Name CPUCLK Flash M0 - M1 RAMs Boot ROM SYSCLK ePIE SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 96 I2CA PMBUSA LINA PERx.LSPCLK SCIA - B SPIA - B CAN Bit Clock CANA - B WDCLK (INTOSC1) Watchdog Timer System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 97: Clock Source And Pll Setup
The following procedure can be used to switch the pins to X1 and X2 mode and enable the oscillator: SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 98 1. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL. To enable XTAL, follow the instructions in the previous sections. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 99: Missing Clock Detection
The missing clock detection (MCD) subsystem detects OSCCLK failure using INTOSC1 as a reference clock. This subsystem only detects complete loss of OSCCLK. Frequency drift is not detected. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 100 OSCCLK source to INTOSC1 using the OSCCLKSRCSEL bits, clear the missing clock condition, then write to the PLL registers. Missing clock detection in enabled at startup. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 101: 32-Bit Cpu Timers
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Section 2.14 are used to configure the timers. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 102: Watchdog Timer
0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55 followed by a write of 0xAA to the WDKEY resets the WDCNTR. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 103: Minimum Window Check
OSCCLK cycles. The falling edge of WDINT triggers a WAKEINT interrupt in the PIE if it is enabled. Because the PIE is edge-triggered, re-enabling the WAKEINT while WDINT is active will not produce a duplicate interrupt. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 104: Watchdog Operation In Low Power Modes
(WDCLK) is suspended. The watchdog remains suspended even within real- time interrupts. Real-Time Run-Free When the CPU is in real-time run-free mode, the watchdog operates as Mode: normal. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 105: 2.10 Low Power Modes
The CPU is now out of STANDBY mode and can resume normal execution SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 106: Halt
Flash to sleep and before putting the device in to low power mode, the application should execute that code from RAM and not from Flash. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 107 Flash/OTP and Pump Power Modes and Wakeup. This applies to all low power modes on this device. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 108: 2.11 Memory Controller Module
RAM block can be enabled or disabled by configuring the specific bit in the local shared RAM access protection registers. Table 2-9 shows the LSx RAM features. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 109: Local Shared Ram
The following is the order of fixed priority for CLA accesses: 1. Data Write 2. Data Read/Program Fetch Figure 2-13 represents the arbitration scheme on global shared memories: SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 110: Arbitration Scheme On Global Shared Memories
‘1.’ If fetch access is done by the CPU to a memory where CPU fetch protection is enabled, a fetch protection violation occurs. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 111 Write accesses from the DMA can be protected by setting the DMAWRPROTx bit of a specific register to ‘1.’ If a write access is done by the DMA to protected memory, a write protection violation occurs. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 112 Also, the address for which the error occurred, gets latched into a register and a flag also gets set in a status register. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 113: Error Handling In Different Scenarios
The following table shows the bit mapping for the ECC/Parity bits when they are read in RAMTEST mode using their respective addresses. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 114: Mapping Of Ecc Bits In Read Data From Ecc/Parity Address Map
None of the masters should access the memory while initialization is taking place. If memory is accessed before RAMINITDONE is set, the memory read/write as well as initialization will not happen correctly. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 115: 2.12 Flash And Otp Memory
Dual Code Security Module (DCSM) to prevent access to the flash by unauthorized persons (refer to DCSM for details) 2.12.2 Flash Tools Texas Instruments provides the following tools for flash: • Code Composer Studio (CCS) - the development environment with integrated flash plugin •...
Page 116: Default Flash Configuration
Figure 2-15. FMC Interface with Core, Bank and Pump Bank0 CPU System Clock Pump Bank1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 117: Flash And Otp And Wakeup Power-Down Modes
SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 118: Flash And Otp Performance
CPU immediately, and every access creates a unique flash bank access. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 119: Flash Prefetch Mode
Using this technique, the overall efficiency of sequential code execution from flash or OTP is improved significantly. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 120 Therefore, the debugger memory window should not be left open for Flash/OTP space when benchmarking the code for performance. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 121: Erase/Program Flash
F021 Flash API library. These functions are written, compiled and validated by Texas Instruments. The flash module contains a flash state machine (FSM) to perform program and erase operations. This section only provides a high level description for these operations, therefore, refer to the C2000 F021 Flash Application Programming Interface (API) Reference Guide for more information.
Page 122: Error Correction Code (Ecc) Protection
The 8-bit output is decoded inside the SECDED module to determine one of three conditions: • No error occurred System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 123 ERR_INTCLR register, the error interrupt will not come again, as this is an edge-based interrupt. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 124 2. Develop an application to test ECC logic using the above data. In this application • Write the 128-bit aligned 19-bit Flash address in FADDR_TEST System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 125: Reserved Locations Within Flash And Otp
4. At the end of the flash configuration code execution, wait eight cycles to let the write instructions propagate through the CPU pipeline. This must be done before the return-from-function call is made. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 126: Dual Code Security Module (Dcsm)
Zone1 is unsecure. Assumption in this case is that user is not using Zone1 so none of the fields, including passwords, in Zone1 USER OTP are programmed by user hence Zone1 will always be unsecure. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 127: Security Levels
Zone2 (Z2OTP_CSMPSWD1) Address Value Address Value Zone_Select_Block0 0x0007802a 0x47ffffff 0x0007822a 0xe3ffffff Zone_Select_Block1 0x0007803a 0xdb7fffff 0x0007823a 0x977fffff Zone_Select_Block2 0x0007804a 0x4bffffff 0x0007824a 0xf1ffffff SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 128 Use the Wait Boot Mode boot option. In this mode, the CPU will be in a loop and hence will not jump to the user application code. Using this BOOTMODE, the user can connect to CCS and debug the code. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 129 • ZxOTP_PSWDLOCK • ZxOTP_CRCLOCK • ZxOTP_BOOTCTRL • ZxOTP_GPREG3 • ZxOTP_EXEONLYRAM • B0_ZxOTP_EXEONLYSECT • ZxOTP_GRABRAM • B0_ZxOTP_GRABSECT • ZxOTP_CSMPSWD0 • ZxOTP_CSMPSWD1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 130 2-18, the final link pointer value becomes All_1 (0xFFFF_FFFF) which selects the Zone-Select-Block1 (also known as the default zone select block). System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 131: Storage Of Zone-Select Bits In Otp
NOTE: Zone select blocks in BANK1 only have Zx-EXEONLYSECT and Zx-GRABSECT as valid configurations. Other locations in zone select block of BANK1 are reserved. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 132: Location Of Zone-Select Block Based On Link-Pointer For Bank0
(16x16 Bits) (16x16 Bits) ZxOTP_CSMPSWD1 ZxOTP_CSMPSWD2 ZxOTP_CSMPSWD3 0x783F0 Zone Select Block n 0x781F0 Zone Select Block n (16x16 Bits) (16x16 Bits) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 133: Location Of Zone-Select Block Based On Link-Pointer For Bank1
(16x16 Bits) (16x16 Bits) Reserved Reserved Reserved 0x785F0 Zone Select Block n 0x787F0 Zone Select Block n (16x16 Bits) (16x16 Bits) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 134 Both the secure RAM block and the secure flash sector have EXEONLY protection enabled. For further usage of these library functions, see the device-specific Boot ROM documentation. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 135: Csm Impact On Other On-Chip Resources
Disclaimer: The Code Security Module (CSM) included on this device was designed to password protect the data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published specifications for the warranty period applicable for this device.
Page 136 To avoid this, user should not keep a memory window with USER OTP address opened in the debugger(CCS) when performing a reset. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 137: Incorporating Code Security In User Applications
A code example is listed for clarity. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 138: Csm Password Match Flow (Pmf)
Secure Zone which needed to be unsecure Write the CSM Password of that Zone into CSMKEY(0/1/2/3) registers. Correct Password ? Zone Unsecure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 139 (PWL) followed by two writes to KEY registers. Figure 2-22 shows how the PMF helps to initialize the security logic registers and disable security logic. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 140: Ecsl Password Match Flow (Pmf)
Write the password into the CSMKEY0/1 registers, corresponding to that Zone. • If the password is correct, the ECSL gets disabled; otherwise, it stays enabled. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 141 // 0x1111222233334444 is used. *ECSL++ = 0x22221111; // Register Z1_CSMKEY0 at 0x5F010 *ECSL++ = 0x44443333; // Register Z1_CSMKEY1 at 0x5F012 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 142: Registers
AccessProtectionRegs ACCESS_PROTECTION_REG 0x0005_F4C0 0x0005_F4FF MemoryErrorRegs MEMORY_ERROR_REGS 0x0005_F500 0x0005_F53F RomWaitStateRegs ROM_WAIT_STATE_REGS 0x0005_F540 0x0005_F541 Flash0CtrlRegs FLASH_CTRL_REGS 0x0005_F800 0x0005_FAFF Flash0EccRegs FLASH_ECC_REGS 0x0005_FB00 0x0005_FB3F System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 143: Access_Protection_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 144: Nmavflg Register
0: No violation. 1: Access violation occured. CPUREAD Non Master CPU Read Access Violation Flag: 0: No violation. 1: Access violation occured. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 145: Nmavset Register
0: No action. 1: CPU Read Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 146: Nmavclr Register
1: CPU Write Access Violation Flag in NMAVFLG register will be cleared. CPUREAD R=0/W=1 0: No action. 1: CPU Read Access Violation Flag in NMAVFLG register will be cleared. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 147: Nmavinten Register
0: CPU Non Master Read Access Violation Interrupt is disabled. 1: CPU Non Master Read Access Violation Interrupt is enabled. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 148: Nmcpurdavaddr Register
Type Reset Description 31-0 NMCPURDAVADDR This register captures the address location for which non master CPU read access vaiolation occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 149: Nmcpuwravaddr Register
Type Reset Description 31-0 NMCPUWRAVADDR This register captures the address location for which non master CPU write access vaiolation occurred. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 150: Nmcpufavaddr Register
Type Reset Description 31-0 NMCPUFAVADDR This register captures the address location for which non master CPU fetch access vaiolation occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 151: Nmdmawravaddr Register
Type Reset Description 31-0 NMDMAWRAVADDR This register captures the address location for which non master DMA write access vaiolation occurred. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 152: Nmcla1Rdavaddr Register
Type Reset Description 31-0 NMCLA1RDAVADDR This register captures the address location for which non master CLA1 read access vaiolation occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 153: Nmcla1Wravaddr Register
Type Reset Description 31-0 NMCLA1WRAVADDR This register captures the address location for which non master CLA1 write access vaiolation occurred. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 154: Nmcla1Favaddr Register
Type Reset Description 31-0 NMCLA1FAVADDR This register captures the address location for which non master CLA1 fetch access vaiolation occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 155: Mavflg Register
0: No violation. 1: Access violation occured. CPUFETCH Master CPU Fetch Access Violation Flag: 0: No violation. 1: Access violation occured. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 156: Mavset Register
0: No action. 1: CPU Fetch Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 157: Mavclr Register
1: CPU Write Access Violation Flag in MAVFLG register will be cleared . CPUFETCH R=0/W=1 0: No action. 1: CPU Fetch Access Violation Flag in MAVFLG register will be cleared. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 158: Mavinten Register
1: CPU Write Access Violation Interrupt is enabled. CPUFETCH 0: CPU Fetch Access Violation Interrupt is disabled. 1: CPU Fetch Access Violation Interrupt is enabled. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 159: Mcpufavaddr Register
Field Type Reset Description 31-0 MCPUFAVADDR This register captures the address location for which master CPU fetch access vaiolation occurred. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 160: Mcpuwravaddr Register
Field Type Reset Description 31-0 MCPUWRAVADDR This register captures the address location for which master CPU write access vaiolation occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 161: Mdmawravaddr Register
Field Type Reset Description 31-0 MDMAWRAVADDR This register captures the address location for which master DMA write access vaiolation occurred. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 162: Clk_Cfg_Regs Registers
Write Type Write Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 163: Clkcfglock1 Register
RESERVED Reserved SYSPLLMULT R/WSOnce Lock bit for SYSPLLMULT register: 0: Respective register is not locked 1: Respective register is locked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 164 1: Respective register is locked. CLKSRCCTL1 R/WSOnce Lock bit for CLKSRCCTL1 register: 0: Respective register is not locked 1: Respective register is locked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 165: Clksrcctl1 Register
NOTE: Ensure no resources are using a clock source prior to disabling it. For example OSCCLKSRCSEL (SYSPLL), AUXOSCCLKSRCSEL (AUXPLL), TMR2CLKSRCSEL (CPUTIMER2) and XCLOCKOUT (XCLKOUT). RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 166 If user wants to re-lock the PLL with INTOSC1 (the back- up clock source) after missing clock is detected, he can do a MCLKCLR and lock the PLL. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 167: Clksrcctl2 Register
01 = External Oscillator (XTAL) 10 = Reserved 11 = Reserved Missing clock detect circuit doesnt have any impact on these bits. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 168: Clksrcctl3 Register
010 = SYSCLK 011 = Reserved 100 = Reserved 101 = INTOSC1 110 = INTOSC2 111 = XTAL OSC o/p clock System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 169: Syspllctl1 Register
1 = SYSPLL is enabled 0 = SYSPLL is powered off. Clock to system is direct feed from OSCCLK SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 170: Syspllmult Register
0000001 Integer Multiplier = 1 0000010 Integer Multiplier = 2 0000011 Integer Multiplier = 3 ..1111111 Integer Multipler = 127 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 171: Syspllsts Register
SYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is locked or not 0 = SYSPLL is not yet locked 1 = SYSPLL is locked SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 172: Sysclkdivsel Register
000000 = /1 000001 = /2 000010 = /4 (default on reset) 000011 = /6 000100 = /8 ..111111 = /126 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 173: Xclkoutdivsel Register
XCLKOUT Divide Select: This bit selects the divider setting for the XCLKOUT. 00 = /1 01 = /2 10 = /4 11 = /8 (default on reset) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 174: Lospcp Register
110,LSPCLK = / 12 111,LSPCLK = / 14 Note: [1] This clock is used as strobe for the SCI and SPI modules. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 175: Mcdcr Register
Write 1" to this bit to clear MCLKSTS bit and reset the missing clock detect circuit." MCLKSTS Missing Clock Status Bit: 0 = OSCCLK Is OK 1 = OSCCLK Detected Missing, CLOCKFAILn Generated SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 176: X1Cnt Register
This will guarantee that the Crystal connected to X1/X2 is powered Up. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 177: Xtalcr Register
X1/X2, user needs to first clear this bit, wait for the oscillator to power up (using X1CNT) and then only switch the clock source to X1/X2 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 178: Cpu_Sys_Regs Registers
Write Type Write Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 179: Cpusyslock1 Register
1: Respective register is locked. GPIOLPMSEL1 R/WSOnce Lock bit for GPIOLPMSEL1 Register: 0: Respective register is not locked 1: Respective register is locked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 180 1: Respective register is locked. PCLKCR3 R/WSOnce Lock bit for PCLKCR3 Register: 0: Respective register is not locked 1: Respective register is locked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 181 Lock bit for PIEVERRADDR Register: 0: Respective register is not locked 1: Respective register is locked. RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 182: Pieverraddr Register
If this register is not initialized, a default error handler at address 0x3fffbe will get executed. Refer to the Boot ROM section for more details on this register. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 183: Pclkcr0 Register
1: Module clock is turned-on RESERVED Reserved CLA1 CLA1 Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 184: Pclkcr2 Register
1: Module clock is turned-on EPWM3 EPWM3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 185 1: Module clock is turned-on EPWM1 EPWM1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 186: Pclkcr3 Register
1: Module clock is turned-on ECAP1 ECAP1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 187: Pclkcr4 Register
1: Module clock is turned-on EQEP1 EQEP1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 188: Pclkcr6 Register
RESERVED Reserved RESERVED Reserved RESERVED Reserved SD1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 189: Pclkcr7 Register
1: Module clock is turned-on SCI_A SCI_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 190: Pclkcr8 Register
1: Module clock is turned-on SPI_A SPI_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 191: Pclkcr9 Register
31-2 RESERVED Reserved RESERVED Reserved I2C_A I2C_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 192: Pclkcr10 Register
1: Module clock is turned-on CAN_A CAN_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 193: Pclkcr13 Register
1: Module clock is turned-on ADC_A ADC_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 194: Pclkcr14 Register
1: Module clock is turned-on CMPSS1 CMPSS1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 195: Pclkcr15 Register
1: Module clock is turned-on PGA1 PGA1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 196: Pclkcr16 Register
0: Module clock is gated-off 1: Module clock is turned-on 15-4 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 197: Pclkcr17 Register
Table 2-70. PCLKCR17 Register Field Descriptions Field Type Reset Description 31-4 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 198: Pclkcr18 Register
Table 2-71. PCLKCR18 Register Field Descriptions Field Type Reset Description 31-4 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 199: Pclkcr19 Register
Reserved RESERVED Reserved RESERVED Reserved LIN_A LIN_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 200: Pclkcr20 Register
31-2 RESERVED Reserved RESERVED Reserved PMBUS_A PMBUS_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 201: Pclkcr21 Register
Reset Description 31-1 RESERVED Reserved DCC_0 DCC Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 202: Lpmcr Register
CPU executes the IDLE instruction (when IDLE instruction is out of EXE Phase of the Pipeline) 00: IDLE Mode 01: STANDBY Mode 1x: HALT Mode System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 203: Gpiolpmsel0 Register
1 pin is connected to LPM circuit GPIO20 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 204 1 pin is connected to LPM circuit GPIO0 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 205: Gpiolpmsel1 Register
1 pin is connected to LPM circuit GPIO52 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 206 1 pin is connected to LPM circuit GPIO32 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 207: Tmr2Clkctl Register
001 = INTOSC1 010 = INTOSC2 011 = XTAL 100 = FLPUMPOSC 101 = FOSCCLK 110 = AUXPLLCLK (Reserved) 111 = reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 208: Rescclr Register
0. Writing a 1 to this bit clears the status bit in RESC to 0 Writing 0 has no effect. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 209: Resc Register
This register is a one-stop shop for the software to know the reset cause for the C28x core. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 210 If this bit is set, indicates that the device was reset by PORn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 211: Cputimer_Regs Registers
Read Type Read Write Type Write Write 1 to clear Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 212: Tim Register
TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD registers. The timer interrupt (TINT) signal is generated. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 213: Prd Register
The PRDH:PRD contents are also loaded into the TIMH:TIM when you set the timer reload bit (TRB) in the Timer Control Register (TCR). SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 214: Tcr Register
PRDH:PRD, and the prescaler counter (PSCH:PSC) is loaded with the value in the timer dividedown register (TDDRH:TDDR). System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 215 1h (R/W) = Reads of 1 indicate that the CPU-timer is stopped. To stop the CPU-timer, set TSS to 1. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 216: Tpr Register
TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit (TRB) is set by software. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 217: Tprh Register
Table 2-87. TPRH Register Field Descriptions Field Type Reset Description 15-8 PSCH See description of TIMERxTPR. TDDRH See description of TIMERxTPR. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 218: Dcc_Regs Registers
Description Read Type Read Read Read Write Type Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 219: Dccgctrl Register
Others: The error signal is enabled DCCENA DCC Enable Starts and stops the operation of the DCC. 0101: Counters are stopped Others: Counters are running SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 220: Dccrev Register
Minor Revision Number Represents minor changes to the module (e.g. enhancements to existing features). The minor revision number for this module. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 221: Dcccntseed0 Register
Contains the seed value that gets loaded into Counter 0 (Clock Source 0). NOTE: Operating the DCC with '0' in the COUNTSEED0 register will result in undefined operation. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 222: Dccvalidseed0 Register
COUNT1 expires. This window is meant to be at least four cycles wide. Do not program a value less than '4' into the VALID0 register. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 223: Dcccntseed1 Register
Contains the seed value that gets loaded into Counter 1 (Clock Source 1). NOTE: Operating the DCC with '0' in the COUNTSEED1 register will result in undefined operation. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 224: Dccstatus Register
Indicates whether or not an error has occurred. Writing a '1' to this bit clears the flag. 0: No errors have occurred. 1: An error has occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 225: Dcccnt0 Register
NOTE: Reads of the counter value may not be exact since the read operation is synchronized to the vbus clock. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 226: Dccvalid0 Register
NOTE: Reads of the counter value may not be exact since the read operation is synchronized to the vbus clock. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 227: Dcccnt1 Register
NOTE: Reads of the counter value may not be exact since the read operation is synchronized to the vbus clock. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 228: Dccclksrc1 Register
1101: Clock Source 13 (ADCCLK) is selected for COUNT1. 1110: Clock Source 14 (WDCLK) is selected for COUNT1. 1111: Clock Source 15 (CANxBITCLK) is selected for COUNT1. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 229: Dccclksrc0 Register
1010: Clock Source 6(Reserved) is selected for COUNT0. 1001: Clock Source 7(Reserved) is selected for COUNT0. All other combinations VCLK is selected for COUNT0. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 230: Dcsm_Bank0_Z1_Regs Registers
Code Description Read Type Read Read Write Type Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 231: B0_Z1_Linkpointer
This is resolved Link-Pointer for Zone1 zone select block USER OTP of Flash BANK0. This is generated by using three physical Link- Pointer values loaded from OTP in Flash BANK0. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 232: Z1_Otpseclock
Z1OTP_JTAGLOCK in OTP. 1111 : JTAG/Emulation access is allowed. Other Value : JTAG/Emulation access not allowed. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 233: Z1_Bootdef_High
Table 2-105. Z1_BOOTDEF_HIGH Register Field Descriptions Field Type Reset Description 31-0 BOOTDEF_HIGH Refer ROM Code and Peripheral Booting section of TRM. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 234: B0_Z1_Linkpointererr
USER OTP in Flash BANK0 0 : No Error. Other : Error on bit positions which is set to 1. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 235: Z1_Bootpin_Config
Table 2-107. Z1_BOOTPIN_CONFIG Register Field Descriptions Field Type Reset Description 31-0 BOOTPIN_CONIFG Refer ROM Code and Peripheral Booting section of TRM. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 236: Z1_Gpreg2
Table 2-108. Z1_GPREG2 Register Field Descriptions Field Type Reset Description 31-0 GPREG2 Refer ROM Code and Peripheral Booting section of TRM. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 237: Z1_Bootdef_Low
Table 2-109. Z1_BOOTDEF_LOW Register Field Descriptions Field Type Reset Description 31-0 BOOTDEF_LOW Refer ROM Code and Peripheral Booting section of TRM. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 238: Z1_Csmkey0
Z1_CSMPSWD0, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 239: Z1_Csmkey1
Z1_CSMPSWD1, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 240: Z1_Csmkey2
Z1_CSMPSWD2, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 241: Z1_Csmkey3
Z1_CSMPSWD3, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 242: Z1_Cr
0 : CSM Passwords are not all zeros. 1 : CSM Passwords are all zero and device is permanently locked. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 243: B0_Z1_Grabsectr
11 : No request for Flash Sector 12 when this zone is UNLOCKED. Else Flash Sector 12 is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 244 11 : No request for Flash Sector 6 when this zone is UNLOCKED. Else Flash Sector 6 is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 245 11 : No request for Flash Sector 0 when this zone is UNLOCKED. Else Flash Sector 0 is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 246: Z1_Grabramr Register
11 : No request for LS5 RAM when this zone is UNLOCKED. Else LS5 RAM is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 247 11 : No request for LS0 RAM when this zone is UNLOCKED. Else LS0 RAM is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 248: B0_Z1_Exeonlysectr Register
0 : Execute-Only protection is enabled for Flash Sector 12 (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for Flash Sector 12 (only if it's allocated to Zone1) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 249 0 : Execute-Only protection is enabled for Flash Sector 4 (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for Flash Sector 4 (only if it's allocated to Zone1) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 250 0 : Execute-Only protection is enabled for Flash Sector 0 (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for Flash Sector 0 (only if it's allocated to Zone1) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 251: Z1_Exeonlyramr
0 : Execute-Only protection is enabled for LS4 RAM (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for LS4 RAM (only if it's allocated to Zone1) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 252 0 : Execute-Only protection is enabled for LS0 RAM (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for LS0 RAM (only if it's allocated to Zone1) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 253: Link Pointer Error For Flash Bank0
Code Description Read Type Read Read Write Type Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 254: B0_Z2_Linkpointer Register
This is resolved Link-Pointer for Zone2 zone select block USER OTP of Flash BANK0. This is generated by using three physical Link- Pointer values loaded from OTP in Flash BANK0. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 255: Z2_Otpseclock
Z2_JATGLOCK in OTP. 1111 : JTAG/Emulation access is allowed. Other Value : JTAG/Emulation access not allowed. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 256: B0_Z2_Linkpointererr Register
USER OTP in Flash BANK0 0 : No Error. Other : Error on bit positions which is set to 1. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 257: Z2_Csmkey0
Z2_CSMPSWD0, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 258: Z2_Csmkey1
Z2_CSMPSWD1, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 259: Z2_Csmkey2
Z2_CSMPSWD2, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 260: Z2_Csmkey3
Z2_CSMPSWD3, programmed in USER OTP (zone gets unlock only when 128 bit password in USER OTP match with value written in four CSMKEY registers.) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 261: Z2_Cr
0 : CSM Passwords are not all zeros. 1 : CSM Passwords are all zero and device is permanently locked. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 262: B0_Z2_Grabsectr
11 : No request for Flash Sector 12 when this zone is UNLOCKED. Else Flash Sector 12 is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 263 11 : No request for Flash Sector 6 when this zone is UNLOCKED. Else Flash Sector 6 is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 264 11 : No request for Flash Sector 0 when this zone is UNLOCKED. Else Flash Sector 0 is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 265: Z2_Grabramr Register
11 : No request for LS5 RAM when this zone is UNLOCKED. Else LS5 RAM is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 266 11 : No request for LS0 RAM when this zone is UNLOCKED. Else LS0 RAM is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 267: B0_Z2_Exeonlysectr
0 : Execute-Only protection is enabled for Flash Sector 12 (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for Flash Sector 12 (only if it's allocated to Zone2) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 268 0 : Execute-Only protection is enabled for Flash Sector 4 (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for Flash Sector 4 (only if it's allocated to Zone2) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 269 0 : Execute-Only protection is enabled for Flash Sector 0 (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for Flash Sector 0 (only if it's allocated to Zone2) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 270: Zone 2 Ram Execute_Only Block Register
0 : Execute-Only protection is enabled for LS4 RAM (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for LS4 RAM (only if it's allocated to Zone2) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 271 0 : Execute-Only protection is enabled for LS0 RAM (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for LS0 RAM (only if it's allocated to Zone2) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 272: Dcsm_Bank1_Z1_Regs Registers
Codes Access Type Code Description Read Type Read Read Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 273: B1_Z1_Linkpointer Register
This is resolved Link-Pointer for Zone1 zone select block USER OTP of Flash BANK1. This is generated by using three physical Link- Pointer values loaded from OTP in Flash BANK1. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 274: B1_Z1_Linkpointererr Register
USER OTP in Flash BANK1 0 : No Error. Other : Error on bit positions which is set to 1. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 275: B1_Z1_Grabsectr Register
11 : No request for Flash Sector 12 when this zone is UNLOCKED. Else Flash Sector 12 is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 276 11 : No request for Flash Sector 6 when this zone is UNLOCKED. Else Flash Sector 6 is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 277 11 : No request for Flash Sector 0 when this zone is UNLOCKED. Else Flash Sector 0 is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 278: B1_Z1_Exeonlysectr Register
0 : Execute-Only protection is enabled for Flash Sector 12 (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for Flash Sector 12 (only if it's allocated to Zone1) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 279 0 : Execute-Only protection is enabled for Flash Sector 4 (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for Flash Sector 4 (only if it's allocated to Zone1) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 280 0 : Execute-Only protection is enabled for Flash Sector 0 (only if it's allocated to Zone1) 1 : Execute-Only protection is disabled for Flash Sector 0 (only if it's allocated to Zone1) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 281: Dcsm_Bank1_Z2_Regs Registers
Codes Access Type Code Description Read Type Read Read Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 282: B1_Z2_Linkpointer Register
This is resolved Link-Pointer for Zone2 zone select block USER OTP of Flash BANK1. This is generated by using three physical Link- Pointer values loaded from OTP in Flash BANK1. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 283: B1_Z2_Linkpointererr Register
USER OTP in Flash BANK1 0 : No Error. Other : Error on bit positions which is set to 1. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 284: B1_Z2_Grabsectr Register
11 : No request for Flash Sector 12 when this zone is UNLOCKED. Else Flash Sector 12 is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 285 11 : No request for Flash Sector 6 when this zone is UNLOCKED. Else Flash Sector 6 is inaccessible if this zone is LOCKED. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 286 11 : No request for Flash Sector 0 when this zone is UNLOCKED. Else Flash Sector 0 is inaccessible if this zone is LOCKED. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 287: B1_Z2_Exeonlysectr Register
0 : Execute-Only protection is enabled for Flash Sector 12 (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for Flash Sector 12 (only if it's allocated to Zone2) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 288 0 : Execute-Only protection is enabled for Flash Sector 4 (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for Flash Sector 4 (only if it's allocated to Zone2) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 289 0 : Execute-Only protection is enabled for Flash Sector 0 (only if it's allocated to Zone2) 1 : Execute-Only protection is disabled for Flash Sector 0 (only if it's allocated to Zone2) SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 290: Dcsm_Common_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 291: Flsem Register
10 TO 00/11 : Code running from Zone2 can perform this transition 10 TO 01 : Not allowed. 01 TO 10 : Not allowed. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 292: B0_Sectstat Register
10 : Sector belongs to Zone2. 11: Sector is un-secure and code running in both zone have full access to it. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 293 10 : Sector belongs to Zone2. 11: Sector is un-secure and code running in both zone have full access to it. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 294 10 : Sector belongs to Zone2. 11: Sector is un-secure and code running in both zone have full access to it. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 295: Ramstat Register
10 : RAM belongs to Zone2. 11: RAM is un-secure and code running in both zone have full access to it. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 296 10 : RAM belongs to Zone2. 11: RAM is un-secure and code running in both zone have full access to it. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 297: B1_Sectstat Register
10 : Sector belongs to Zone2. 11: Sector is un-secure and code running in both zone have full access to it. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 298 10 : Sector belongs to Zone2. 11: Sector is un-secure and code running in both zone have full access to it. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 299 10 : Sector belongs to Zone2. 11: Sector is un-secure and code running in both zone have full access to it. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 300: Secerrstat Register
0: No error has occurred in the load of security information from USER-OTP 1: Error has occurred in the load of security information from USER- System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 301: Secerrclr Register
R=0/W=1 A write of '1' clears the SECERRSTST.ERR bit. Write of '0' is ignored. This bit always reads back '0'. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 302: Secerrfrc Register
R=0/W=1 A write of '1' sets the SECERRSTST.ERR bit. Write of '0' is ignored. This bit always reads back '0'. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 303: Dcsm_Common2_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 304: Dev_Cfg_Regs Registers
Write Write WOnce Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 305: Partidl Register
0 = Engineering sample (TMX) 1 = Pilot production (TMP) 2 = Fully qualified (TMS) RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 306: Partidh Register
0x3 - DELFINO DUAL CORE 0x4 - DELFINO SINGLE CORE 0x5 - PICCOLO SINGLE CORE Other values Reserved RESERVED Reserved RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 307: Revid Register
REVID R=0-0h R-0h Table 2-160. REVID Register Field Descriptions Field Type Reset Description 31-16 RESERVED Reserved 15-0 REVID Device Revision SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 308: Fuseerr Register
[1] 10101 means a single-bit error during autoload. Since this gets corrected by the ECC mechanism, this value shouldn't be treated as an error condition. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 309: Softpres0 Register
Reserved RESERVED Reserved CPU1_CLA1 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 310: Softpres2 Register
0: Module reset is determined by the normal device reset structure EPWM1 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 311: Softpres3 Register
0: Module reset is determined by the normal device reset structure ECAP1 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 312: Softpres4 Register
0: Module reset is determined by the normal device reset structure EQEP1 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 313: Softpres6 Register
RESERVED Reserved RESERVED Reserved 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 314: Softpres7 Register
0: Module reset is determined by the normal device reset structure SCI_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 315: Softpres8 Register
0: Module reset is determined by the normal device reset structure SPI_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 316: Softpres9 Register
Reserved RESERVED Reserved I2C_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 317: Softpres10 Register
0: Module reset is determined by the normal device reset structure CAN_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 318: Softpres13 Register
0: Module reset is determined by the normal device reset structure ADC_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 319: Softpres14 Register
0: Module reset is determined by the normal device reset structure CMPSS1 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 320: Softpres15 Register
0: Module reset is determined by the normal device reset structure PGA1 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 321: Softpres16 Register
0: Module reset is determined by the normal device reset structure 15-4 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 322: Softpres17 Register
Table 2-175. SOFTPRES17 Register Field Descriptions Field Type Reset Description 31-4 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 323: Softpres18 Register
Table 2-176. SOFTPRES18 Register Field Descriptions Field Type Reset Description 31-4 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 324: Softpres19 Register
Reserved RESERVED Reserved LIN_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 325: Softpres20 Register
Reserved RESERVED Reserved PMBUS_A 1: Module is under reset 0: Module reset is determined by the normal device reset structure SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 326: Softpres21 Register
R=0-0h R-0h R-0h Table 2-179. SOFTPRES21 Register Field Descriptions Field Type Reset Description 31-2 RESERVED Reserved RESERVED Reserved RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 327: Tap_Status Register
POTAP* output to the 0:TLR, 1:IDLE, 2:SELECTDR, 3:CAPDR, 4:SHIFTDR, 5:EXIT1DR, 6:PAUSEDR, 7:EXIT2DR, 8:UPDTDR, 9:SLECTIR, 10:CAPIR, 11:SHIFTIR, 12:EXIT1IR, 13:PAUSEIR, 14:EXIT2IR, 15:UPDTIR, SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 328: Dma_Cla_Src_Sel_Regs Registers
Read Write Type Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 329: Cla1Tasksrcsellock Register
SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 330: Dmachsrcsellock Register
SYSRSn. Write of 0 to any bit of this register has no effect [2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 331: Cla1Tasksrcsel1 Register
Selects the Trigger Source for TASK3 of CLA1 15-8 TASK2 Selects the Trigger Source for TASK2 of CLA1 TASK1 Selects the Trigger Source for TASK1 of CLA1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 332: Cla1Tasksrcsel2 Register
Selects the Trigger Source for TASK7 of CLA1 15-8 TASK6 Selects the Trigger Source for TASK6 of CLA1 TASK5 Selects the Trigger Source for TASK5 of CLA1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 333: Dmachsrcsel1 Register
Selects the Trigger and Sync Source CH3 of DMA 15-8 Selects the Trigger and Sync Source CH2 of DMA Selects the Trigger and Sync Source CH1 of DMA SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 334: Dmachsrcsel2 Register
Reserved 15-8 Selects the Trigger and Sync Source CH6 of DMA Selects the Trigger and Sync Source CH5 of DMA System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 335: Flash_Ctrl_Regs Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 336: Frdcntl Register
Note: The required wait states for each SYSCLK frequency can be found in the device data manual. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 337: Fbac Register
Note: The prescaled clock used for the BAGP down counter is a clock divided by 16 from input SYSCLK. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 338: Fbfallback Register
01 Standby (Sense amplifiers disabled, but sense reference enabled) 10 Reserved 11 Active (Both sense amplifiers and sense reference enabled) System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 339: Fbprdy Register
0 Bank 0 is not ready. 1 Bank 0 is in active power mode and is ready for access. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 340: Fpac1 Register
Note for devices with multiple flash banks: As the pump is shared between flash banks, if an access is made either bank, the value of this bit changes to 1 (active). System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 341: Fpac2 Register
Note: The PAGP down counter is clocked by the same prescaled clock as the BAGP down counter which is divided by 16 of input SYSCLK. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 342: Fmstat Register
Invalid Data. When set, this bit indicates that the user attempted to program a "1" where a "0" was already present. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 343 RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 344: Frd_Intf_Ctrl Register
Prefetch enable. 0 A value of 0 disables the prefetch mechanism. 1 A value of 1 enables the pre-fetch mechanism. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 345: Flash_Ecc_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 346: Ecc_Enable Register
Reserved 15-4 RESERVED Reserved ENABLE ECC enable. A value of 0xA would enable ECC. Any other value would disable ECC. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 347: Single_Err_Addr_Low Register
ERR_ADDR_L 64-bit aligned address at which a single bit error occurred in the lower 64-bits of a 128-bit aligned memory. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 348: Single_Err_Addr_High Register
ERR_ADDR_H 64-bit aligned address at which a single bit error occurred in the upper 64-bits of a 128-bit aligned memory. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 349: Unc_Err_Addr_Low Register
31-0 UNC_ERR_ADDR_L 64-bit aligned address at which an uncorrectable error occurred in the lower 64-bits of a 128-bit aligned memory. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 350: Unc_Err_Addr_High Register
31-0 UNC_ERR_ADDR_H 64-bit aligned address at which an uncorrectable error occurred in the upper 64-bits of a 128-bit aligned memory. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 351: Err_Status Register
64bits of a 128-bit aligned address. Cleared by writing a 1 to UNC_ERR_L_CLR bit of ERR_STATUS_CLR register. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 352 So, in case of multiple single bit error, the status would correspond to the last error which occured. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 353: Err_Pos Register
ERR_TYPE indicates a check bit error, the error position could range from 0 to 7, else it could range from 0 to 63. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 354: Err_Status_Clr Register
Fail on 0 clear. Writing a 1 to this bit will clear the FAIL_0_L bit of ERR_STATUS register. Writes of 0 have no effect. Read returns 0. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 355: Err_Cnt Register
(irrespective of whether threshold is met or not) using "Single Err Int Clear" bit. This is applicable for ECC logic test mode and normal operational mode. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 356: Err_Threshold Register
When the ERR_CNT value equals the THRESHOLD value and a single bit error occurs, SINGLE_ERR_INT flag is set, and an interrupt is fired. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 357: Err_Intflg Register
SINGLE_ERR_INT flag is set and SINGLE_ERR_INT interrupt is fired. When SINGLE_ERR_INTCLR bit of ERR_INTCLR register is written a value of 1 this bit is cleared. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 358: Err_Intclr Register
Single bit error interrupt flag clear. Writing a 1 to this bit will clear SINGLE_ERR_INT_FLG. Writes of 0 have no effect. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 359: Fdatah_Test Register
FDATAH High double word of selected 64-bit data. User-configurable bits 63:32 of the selected data block in ECC test mode. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 360: Fdatal_Test Register
FDATAL Low double word of selected 64-bit data. User-configurable bits 31:0 of the selected data block in ECC test mode. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 361: Faddr_Test Register
(to provide byte address) and ignore the three least significant bits of the address and write the bits 15:3 in remaining address bits in this field. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 362: Fecc_Test Register
Reserved 8-bit ECC for selected 64-bit data. User-configurable ECC bits of the selected 64-bit data block in ECC test mode. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 363: Fecc_Ctrl Register
1 Selects the ECC block on bits [127:64] of bank data. ECC_TEST_EN ECC test mode enable. 0 ECC test mode disabled 1 ECC test mode enabled SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 364: Fouth_Test Register
31-0 DATAOUTH High double word test data out. Holds bits 63:32 of the data out of the selected ECC block. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 365: Foutl_Test Register
31-0 DATAOUTL Low double word test data out. Holds bits 31:0 of the data out of the selected ECC block. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 366: Fecc_Status Register
SINGLE_ERR Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single bit error. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 367: Mem_Cfg_Regs Registers
Table 2-222. MEM_CFG_REGS Access Type Codes Access Type Code Description Read Type Read Read Write Type Write Write WSOnce Write SOnce Set once SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 368 Table 2-222. MEM_CFG_REGS Access Type Codes (continued) Access Type Code Description Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 369: Dxlock Register
0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 370: Dxcommit Register
DxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 371: Dxaccprot0 Register
Type Reset Description 31-26 RESERVED Reserved RESERVED Reserved RESERVED Reserved 23-18 RESERVED Reserved RESERVED Reserved RESERVED Reserved 15-0 RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 372: Dxtest Register
01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 373: Dxinit Register
0: None. 1: Start RAM Initialization. INIT_M0 R=0/W=1 RAM Initialization control for M0 RAM: 0: None. 1: Start RAM Initialization. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 374: Dxinitdone Register
1: RAM Initialization has completed. INITDONE_M0 RAM Initialization status for M0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 375: Lsxlock Register
0: Write to ACCPROT, TEST, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT, CLAPGM and Mselect fields are blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 376 0: Write to ACCPROT, TEST, INIT, CLAPGM and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT, CLAPGM and Mselect fields are blocked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 377: Lsxcommit Register
LSxLOCK register. 1: Write to ACCPROT, TEST, INIT, CLAPGM and Mselect fields are permanently blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 378 LSxLOCK register. 1: Write to ACCPROT, TEST, INIT, CLAPGM and Mselect fields are permanently blocked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 379: Lsxmsel Register
01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 380 01: Memory is shared between CPU and CLA1 if CLAPGM_LSx bit in LSxCLAPGM register is programmed as '0'. 10: Reserved. 11: Reserved. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 381: Lsxclapgm Register
1: CLA Program memory. CLAPGM_LS0 Selects LS0 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 382: Lsxaccprot0 Register
1: CPU Writes are blocked. FETCHPROT_LS1 Fetch Protection For LS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 383 1: CPU Writes are blocked. FETCHPROT_LS0 Fetch Protection For LS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 384: Lsxaccprot1 Register
1: CPU Writes are blocked. FETCHPROT_LS5 Fetch Protection For LS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 385 1: CPU Writes are blocked. FETCHPROT_LS4 Fetch Protection For LS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 386: Lsxtest Register
01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 387 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 388: Lsxinit Register
0: None. 1: Start RAM Initialization. INIT_LS0 R=0/W=1 RAM Initialization control for LS0 RAM: 0: None. 1: Start RAM Initialization. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 389: Lsxinitdone Register
1: RAM Initialization is done. INITDONE_LS0 RAM Initialization status for LS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 390: Gsxlock Register
0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 391: Gsxcommit Register
GSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 392 GSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 393: Gsxaccprot0 Register
15-11 RESERVED Reserved DMAWRPROT_GS1 DMA WR Protection For GS1 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 394 1: CPU Writes are blocked. FETCHPROT_GS0 Fetch Protection For GS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 395: Gsxaccprot1 Register
Reserved RESERVED Reserved 15-11 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 396: Gsxaccprot2 Register
Reserved RESERVED Reserved 15-11 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 397: Gsxaccprot3 Register
Reserved RESERVED Reserved 15-11 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 398: Gsxtest Register
01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 399 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 400: Gsxinit Register
0: None. 1: Start RAM Initialization. INIT_GS0 R=0/W=1 RAM Initialization control for GS0 RAM: 0: None. 1: Start RAM Initialization. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 401: Gsxinitdone Register
1: RAM Initialization is done. INITDONE_GS0 RAM Initialization status for GS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 402: Msgxlock Register
CPUTOCLA1 RAM: 0: Write to TEST, INIT fields are allowed. 1: Write to TEST, INIT fields are blocked. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 403: Msgxcommit Register
0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 404: Msgxtest Register
01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 405: Msgxinit Register
1: Start RAM Initialization. INIT_CPUTOCLA1 R=0/W=1 RAM Initialization control for CPUTOCLA1 MSG RAM: 0: None. 1: Start RAM Initialization. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 406: Msgxinitdone Register
RAM Initialization status for CPUTOCLA1 MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 407: Memory_Error_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 408: Ucerrflg Register
1: Uncorrectable error occurred during DMA read. CPURDERR CPU Uncorrectable Read Error Flag 0: No Error. 1: Uncorrectable error occurred during CPU read. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 409: Ucerrset Register
0: No action. 1: CPU Read Error Flag in UCERRFLG register will be set and interrupt will be generated if enabled.. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 410: Ucerrclr Register
1: DMA Read Error Flag in UCERRFLG register will be cleared . CPURDERR R=0/W=1 0: No action. 1: CPU Read Error Flag in UCERRFLG register will be cleared. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 411: Uccpureaddr Register
Reset Description 31-0 UCCPUREADDR This register captures the address location for which CPU read/fetch access resulted in uncorrectable ECC/Parity error. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 412: Ucdmareaddr Register
Reset Description 31-0 UCDMAREADDR This register captures the address location for which DMA read access resulted in uncorrectable Parity error. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 413: Uccla1Readdr Register
Reset Description 31-0 UCCLA1READDR This register captures the address location for which CLA1 read/fetch access resulted in uncorrectable Parity error. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 414: Cerrflg Register
1: Correctable error occurred during DMA read. CPURDERR CPU Correctable Read Error Flag 0: No Error. 1: Correctable error occurred during CPU read. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 415: Cerrset Register
0: No action. 1: CPU Read Error Flag in CERRFLG register will be set and interrupt will be generated if enabled.. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 416: Cerrclr Register
1: DMA Read Error Flag in CERRFLG register will be cleared . CPURDERR R=0/W=1 0: No action. 1: CPU Read Error Flag in CERRFLG register will be cleared. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 417: Ccpureaddr Register
Reset Description 31-0 CCPUREADDR This register captures the address location for which CPU read/fetch access resulted in correctable ECC error. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 418: Cerrcnt Register
Table 2-264. CERRCNT Register Field Descriptions Field Type Reset Description 31-0 CERRCNT This register holds the count of how many times correctable error occurred. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 419: Cerrthres Register
CERRTHRES When value in CERRCNT register is greater than value configured in this register, corretable interrupt gets generated, if enabled. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 420: Ceintflg Register
0: Total correctable errors < Threshold value configured in CERRTHRES register. 1: Total correctable errors >= Threshold value configured in CERRTHRES register. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 421: Ceintclr Register
RESERVED Reserved CEINTCLR R=0/W=1 0: No action. 1: Total corrected error count exceeded flag in CEINTFLG register will be cleared. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 422: Ceintset Register
1: Total corrected error count exceeded flag in CEINTFLG register will be set and interrupt will be generated if enabled. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 423: Ceinten Register
Description 31-16 RESERVED Reserved 15-1 RESERVED Reserved CEINTEN 0: Correctable Error Interrupt is disabled. 1: Correctable Error Interrupt is enabled. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 424: Nmi_Intrupt_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 425: Nmicfg Register
NMI to the CPU. The boot ROM sets this bit at start-up. It can only be cleared by a system reset. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 426: Nmiflg Register
NMIFLGCLR register. 0h (R/W) = No uncorrectable error detected 1h (R/W) = Uncorrectable error detected System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 427 NMIFLGCLR register. No further NMIs are generated until this flag is cleared. 0h (R/W) = No NMI generated 1h (R/W) = NMI generated SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 428: Nmiflgclr Register
NMIINT R=0/W=1 Clear the NMIINT flag. This flag should only be cleared after all other active flags have been cleared. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 429: Nmiflgfrc Register
FLUNCERR R=0/W=1 Set the FLUNCERR flag. RAMUNCERR R=0/W=1 Set the RAMUNCERR flag. CLOCKFAIL R=0/W=1 Set the CLOCKFAIL flag. RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 430: Nmiwdcnt Register
If all NMI flags are cleared, the counter will reset to zero and stop counting until another NMI flag is set. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 431: Nmiwdprd Register
These bits specify the period of the NMI watchdog timer in SYSCLK cycles. Writing a period value that is smaller than the current counter value will immediately force a reset (NMIWDRS). SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 432: Nmishdflg Register
Shadow PIEVECTERR flag RESERVED Reserved RESERVED Reserved FLUNCERR Shadow FLUNCERR flag RAMUNCERR Shadow RAMUNCERR flag CLOCKFAIL Shadow CLOCKFAIL flag RESERVED Reserved System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 433: Periph_Ac_Regs Registers
CLB3 Master Access Control Register EALLOW CLB4_AC CLB4 Master Access Control Register EALLOW CLA1PROMCRC_AC CLA1PROMCRC Master Access Control EALLOW Register SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 434: Periph_Ac_Regs Access Type Codes
Read Write Type Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 435: Adca_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 436: Adcb_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 437: Adcc_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 438: Cmpss1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 439: Cmpss2_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 440: Cmpss3_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 441: Cmpss4_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 442: Cmpss5_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 443: Cmpss6_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 444: Cmpss7_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 445: Daca_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 446: Dacb_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 447: Pga1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 448: Pga2_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 449: Pga3_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 450: Pga4_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 451: Pga5_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 452: Pga6_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 453: Pga7_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 454: Epwm1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 455: Epwm2_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 456: Epwm3_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 457: Epwm4_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 458: Epwm5_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 459: Epwm6_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 460: Epwm7_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 461: Epwm8_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 462: Eqep1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 463: Eqep2_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 464: Ecap1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 465: Ecap2_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 466: Ecap3_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 467: Ecap4_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 468: Ecap5_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 469: Ecap6_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 470: Ecap7_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 471: Sdfm1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 472: Clb1_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 473: Clb2_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 474: Clb3_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 475: Clb4_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 476: Cla1Promcrc_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 477: Spia_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 478: Spib_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 479: Pmbus_A_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 480: Lin_A_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 481: Dcana_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 482: Dcanb_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 483: Fsiatx_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 484: Fsiarx_Ac
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 485: Hrpwm_A_Ac Register
10: Protected RD Access such that FIFOs, Clear on read registers are not changed + No Write Access 01: Reserved 00: No Read/Write Access to peripheral SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 486: Periph_Ac_Lock Register
1: Access Control registers are Read Only 0: Read/Write Access allowed to Access Control registers. Writing '1' sets the bit, writing '0' has no effect. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 487: Pie_Ctrl_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 488: Piectrl Register
All ePIE registers (PIEACK, PIEIFR, PIEIER) can be accessed even when the ePIE block is disabled. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 489: Pieack Register
R/W=1 Acknowledge PIE Interrupt Group 3 ACK2 R/W=1 Acknowledge PIE Interrupt Group 2 ACK1 R/W=1 Acknowledge PIE Interrupt Group 1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 490: Pieier1 Register
INTx4 Enable for Interrupt 1.4 INTx3 Enable for Interrupt 1.3 INTx2 Enable for Interrupt 1.2 INTx1 Enable for Interrupt 1.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 491: Pieifr1 Register
INTx4 Flag for Interrupt 1.4 INTx3 Flag for Interrupt 1.3 INTx2 Flag for Interrupt 1.2 INTx1 Flag for Interrupt 1.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 492: Pieier2 Register
INTx4 Enable for Interrupt 2.4 INTx3 Enable for Interrupt 2.3 INTx2 Enable for Interrupt 2.2 INTx1 Enable for Interrupt 2.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 493: Pieifr2 Register
INTx4 Flag for Interrupt 2.4 INTx3 Flag for Interrupt 2.3 INTx2 Flag for Interrupt 2.2 INTx1 Flag for Interrupt 2.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 494: Pieier3 Register
INTx4 Enable for Interrupt 3.4 INTx3 Enable for Interrupt 3.3 INTx2 Enable for Interrupt 3.2 INTx1 Enable for Interrupt 3.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 495: Pieifr3 Register
INTx4 Flag for Interrupt 3.4 INTx3 Flag for Interrupt 3.3 INTx2 Flag for Interrupt 3.2 INTx1 Flag for Interrupt 3.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 496: Pieier4 Register
INTx4 Enable for Interrupt 4.4 INTx3 Enable for Interrupt 4.3 INTx2 Enable for Interrupt 4.2 INTx1 Enable for Interrupt 4.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 497: Pieifr4 Register
INTx4 Flag for Interrupt 4.4 INTx3 Flag for Interrupt 4.3 INTx2 Flag for Interrupt 4.2 INTx1 Flag for Interrupt 4.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 498: Pieier5 Register
INTx4 Enable for Interrupt 5.4 INTx3 Enable for Interrupt 5.3 INTx2 Enable for Interrupt 5.2 INTx1 Enable for Interrupt 5.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 499: Pieifr5 Register
INTx4 Flag for Interrupt 5.4 INTx3 Flag for Interrupt 5.3 INTx2 Flag for Interrupt 5.2 INTx1 Flag for Interrupt 5.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 500: Pieier6 Register
INTx4 Enable for Interrupt 6.4 INTx3 Enable for Interrupt 6.3 INTx2 Enable for Interrupt 6.2 INTx1 Enable for Interrupt 6.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 501: Pieifr6 Register
INTx4 Flag for Interrupt 6.4 INTx3 Flag for Interrupt 6.3 INTx2 Flag for Interrupt 6.2 INTx1 Flag for Interrupt 6.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 502: Pieier7 Register
INTx4 Enable for Interrupt 7.4 INTx3 Enable for Interrupt 7.3 INTx2 Enable for Interrupt 7.2 INTx1 Enable for Interrupt 7.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 503: Pieifr7 Register
INTx4 Flag for Interrupt 7.4 INTx3 Flag for Interrupt 7.3 INTx2 Flag for Interrupt 7.2 INTx1 Flag for Interrupt 7.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 504: Pieier8 Register
INTx4 Enable for Interrupt 8.4 INTx3 Enable for Interrupt 8.3 INTx2 Enable for Interrupt 8.2 INTx1 Enable for Interrupt 8.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 505: Pieifr8 Register
INTx4 Flag for Interrupt 8.4 INTx3 Flag for Interrupt 8.3 INTx2 Flag for Interrupt 8.2 INTx1 Flag for Interrupt 8.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 506: Pieier9 Register
INTx4 Enable for Interrupt 9.4 INTx3 Enable for Interrupt 9.3 INTx2 Enable for Interrupt 9.2 INTx1 Enable for Interrupt 9.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 507: Pieifr9 Register
INTx4 Flag for Interrupt 9.4 INTx3 Flag for Interrupt 9.3 INTx2 Flag for Interrupt 9.2 INTx1 Flag for Interrupt 9.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 508: Pieier10 Register
INTx4 Enable for Interrupt 10.4 INTx3 Enable for Interrupt 10.3 INTx2 Enable for Interrupt 10.2 INTx1 Enable for Interrupt 10.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 509: Pieifr10 Register
INTx4 Flag for Interrupt 10.4 INTx3 Flag for Interrupt 10.3 INTx2 Flag for Interrupt 10.2 INTx1 Flag for Interrupt 10.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 510: Pieier11 Register
INTx4 Enable for Interrupt 11.4 INTx3 Enable for Interrupt 11.3 INTx2 Enable for Interrupt 11.2 INTx1 Enable for Interrupt 11.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 511: Pieifr11 Register
INTx4 Flag for Interrupt 11.4 INTx3 Flag for Interrupt 11.3 INTx2 Flag for Interrupt 11.2 INTx1 Flag for Interrupt 11.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 512: Pieier12 Register
INTx4 Enable for Interrupt 12.4 INTx3 Enable for Interrupt 12.3 INTx2 Enable for Interrupt 12.2 INTx1 Enable for Interrupt 12.1 System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 513: Pieifr12 Register
INTx4 Flag for Interrupt 12.4 INTx3 Flag for Interrupt 12.3 INTx2 Flag for Interrupt 12.2 INTx1 Flag for Interrupt 12.1 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 514: Rom_Prefetch_Regs Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 515: Romprefetch Register
0: Prefetch is disabled for secure ROM and boot ROM. 1: Prefetch is enabled for secure ROM and boot ROM. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 516: Rom_Wait_State_Regs Registers
Access Type Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 517: Romwaitstate Register
0: ROM Wait State is enabled. CPU accesses to ROM are are 1- wait. 1: ROM Wait State is disabled. CPU accesses to ROM are 0-wait. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 518: Wd_Regs Registers
Description Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 519: Scsr Register
The bit will remain in this state until the next system reset. Reads of this bit return its current value. Writing a 0 to this bit has no effect. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 520: Wdcntr Register
WDINTEN bit in the SCSR register. If the correct value is written to the WDKEY register, this counter is reset to zero. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 521: Wdkey Register
Writing other values has no effect. Reads of this register return the value of the WDCR register. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 522: Wdcr Register
During any write to this register, these bits must be written with the value 101 (binary). Writing any other value will immediately trigger the watchdog reset or interrupt. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 523 5h (R/W) = WDCLK = PREDIVCLK / 16 6h (R/W) = WDCLK = PREDIVCLK / 32 7h (R/W) = WDCLK = PREDIVCLK / 64 SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 524: Wdwcr Register
If the counter is reset via the WDKEY register before the counter value reaches the value in this register, the watchdog immediately triggers a reset or interrupt. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 525: Xint_Regs Registers
Code Description Read Type Read Read Write Type Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 526: Xint1Cr Register
10: Interrupt is selected as negative edge triggered 11: Interrupt is selected as positive or negative edge triggered RESERVED Reserved ENABLE 0: Interrupt Disabled 1: Interrupt Enabled System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 527: Xint2Cr Register
10: Interrupt is selected as negative edge triggered 11: Interrupt is selected as positive or negative edge triggered RESERVED Reserved ENABLE 0: Interrupt Disabled 1: Interrupt Enabled SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 528: Xint3Cr Register
10: Interrupt is selected as negative edge triggered 11: Interrupt is selected as positive or negative edge triggered RESERVED Reserved ENABLE 0: Interrupt Disabled 1: Interrupt Enabled System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 529: Xint4Cr Register
10: Interrupt is selected as negative edge triggered 11: Interrupt is selected as positive or negative edge triggered RESERVED Reserved ENABLE 0: Interrupt Disabled 1: Interrupt Enabled SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 530: Xint5Cr Register
10: Interrupt is selected as negative edge triggered 11: Interrupt is selected as positive or negative edge triggered RESERVED Reserved ENABLE 0: Interrupt Disabled 1: Interrupt Enabled System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 531: Xint1Ctr Register
The counter is a read only register and can only be reset to zero by a valid interrupt edge or by reset. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 532: Xint2Ctr Register
The counter is a read only register and can only be reset to zero by a valid interrupt edge or by reset. System Control SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 533: Xint3Ctr Register
The counter is a read only register and can only be reset to zero by a valid interrupt edge or by reset. SPRUI33 – November 4 2015 – Revised January 2017 System Control Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 534: Rom Code And Peripheral Booting
..............Device Reset and Exception Handling ..................Boot ROM Description ............Application Notes for Using the Bootloaders ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 535: Introduction
Users have the option to customize the boot modes supported as well as the boot mode select pins. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 536: Configuring Alternate Boot Mode Pins
If any other BMSPs are not set to 0xFF, then setting a BMSP to 0xFF will disable that particular BMSP. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 537: Configuring Alternate Boot Mode Options
Refer to Boot Mode Example Use Cases for examples on how to use the BOOTPIN_CONFIG and BOOTDEF values. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 538: Boot Mode Example Use Cases
1. Program the BOOTPIN_CONFIG location in OTP as follows: • Set BOOTPIN_CONFIG.BMSP0 to a user specified GPIO, such as 0x0 for GPIO0 ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 539: One Boot Pin Boot Table Result
CAN Boot (0x02) Flash Boot (0x03) Refer to Entry Points for the available alternative entry point addresses. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 540: Device Boot Flow Diagrams
Device Calibration Clear Reset Cause Register bits for POR and XRS Is Debugger Connected? Standalone Emulation Boot Boot ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 541: Emulation Boot Flow Diagram
Branch to Application Code Decode flash BOOTDEF options Branch to Flash Entry Point SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 542: Standalone Boot Flow Diagram
Branch to Application Code Decode flash BOOTDEF options Branch to Flash Entry Point ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 543: Device Reset And Exception Handling
NOTE: The above NMI errors are logged into a RAM variable for an application to read it when it starts. Refer to Boot Status Information for more details on the boot status information. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 544: Boot Rom Description
Flash (Option 2) 0x0008 EFF0 Flash (Option 3) 0x0009 0000 Flash (Option 4) 0x0009 EFF0 0x003F 1800 ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 545: Wait Points
Check the data manual to determine if these are available for your device part number. If not available, treat these sections as reserved. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 546: Rom Tables
0x0000 f9fc _CLAatan2TableEnd 0x0000 f9fc _CLAasinTable 0x0000 fa00 _CLAacosinHalfPITable 0x0000 fb86 _CLAasinTableEnd 0x0000 fb86 _CLAacosinTable 0x0000 fb8a ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 547: Boot Modes
TI recommends using wait boot when using a debugger to avoid any JTAG complications. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 548: Overview Of Sci Bootloader Operation
3. The host may then handshake with the loaded application to set the SCI baud rate register to the desired high baud rate. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 549: Spi Loader
Xicor X25320 (4Kx8) and Xicor X25256 (32Kx8) SPI serial SPI EEPROMs and the Atmel AT25F1024A serial flash. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 550: Spi 8-Bit Data Stream
Step 7. The next two words makeup the 32-bit entry point address where execution will continue after ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 551: Data Transfer From Eeprom Flow
16-bit base address architecture. Figure 3-8. EEPROM Device at Address 0x50 I2CA_SDA Control subsystem I2CA_SCL EEPROM Slave Address 0x50 SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 552: Overview Of I2C Boot Function
I2C messages until the application software signals that it is past the bootloader portion of initialization. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 553: Random Read
0 0 0 1 0 Device Address Address Device DATA BYTE 1 DATA BYTE 2 Address Pointer, MSB Pointer, LSB Address SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 554: Sequential Read
First word of the second block in the source being loaded … Last word of the last block of the source being loaded (More sections if required) ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 555: Parallel Gpio Bootloader Handshake Protocol
SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 556: Parallel Gpio Mode - Host Transfer Flow
(MSB). It then combines the MSB and LSB into a single 16-bit value to be passed back to the calling routine. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 557: Bit Parallel Getword Function
The host can download a kernel to reconfigure the CAN if higher data throughput is desired. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 558: Overview Of Can-A Bootloader Operation
Data for this section. Last word of the first block of the source being loaded = 0xAABB ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 559: Boot Data Stream Structure
Execution will then continue at the entry point address as determined by the input data stream contents. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 560: Lsb/Msb Loading Sequence In 8-Bit Data Stream
03 00 04 00 05 00 02 00 ; 0x0002 - 2nd block consists of 2 16-bit words ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 561: Gpio Assignments
Flash – Option 2 0x23 Bank 0, Sector 14 (0x0008EFF0) Flash – Option 3 0x43 Bank 1, Sector 0 (0x00090000) SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 562: Dcsm Usage
This section explains how the bit field values from the user-configurable DCSM OTP location, Z1-OTP- BOOT-GPREG2, are decoded by the boot ROM after DCSM initialization is complete. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 563: Clock Initialization
Boot ROM stores the boot status information in a RAM location so that the user application can look at this boot status and take the necessary actions per the application’s needs to handle these events. SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 564: Rom Version
The ROM revision and release date information is stored at the ROM locations specified in this section. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 565: Application Notes For Using The Bootloaders
Convert all sections into bootable form (use instead of a SECTIONS directive) -sci8 Specify the source of the bootloader table as the SCI-A port, 8-bit mode SPRUI33 – November 4 2015 – Revised January 2017 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 566 GPIO in 8-bit mode. Select ASCII-Hex as the output format. ROM Code and Peripheral Booting SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 567: Control Law Accelerator (Cla)
................. CLA, DMA, and CPU Arbitration ................CLA Configuration and Debug ......................Pipeline ....................Instruction Set ......................Registers SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 568: Control Law Accelerator (Cla) Overview
– The CLA, on reset, is the secondary master for all peripherals which can have either the CLA or DMA as their secondary master. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 569: Cla Block Diagram
MR3(32) PDB ± Program Data Bus MAR0(16) MAR1(16) CPU Read Data Bus Copyright © 2017, Texas Instruments Incorporated SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 570: Cla Interface
CPU. The CLA can perform reads but writes by the CLA are ignored. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 571: Cla Memory Bus
ADC value. The CLA pipeline activity for this scenario is shown in Section 4.5. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 572: Cla Tasks And Interrupt Vectors
ADCC3_INT ADCC4_INT ADCC_EVT_INT 28:16 Reserved XINT1 XINT2 XINT3 XINT4 XINT5 35:34 Reserved EPWM1INT EPWM2INT EPWM3INT EPWM4INT EPWM5INT EPWM6INT Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 573 Reserved SPITXINTA SPIRXINTA SPITXINTB SPIRXINTB 116:113 Reserved LINA_INT1 LINA_INT0 120:119 Reserved CLA1PROMCRC Reserved FSITX_INT1 FSITX_INT2 FSIRX_INT1 FSIRX_INT2 CLB1INT SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 574 3. The CLA executes instructions until the MSTOP instruction is found. This indicates the end of the task. 4. The MIRUN bit is cleared. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 575: Cla Software Interrupt To Cpu
CPU to CLA1 Message RAM: The following accesses are allowed: – CPU reads and writes – CPU.CLA1 reads SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 576 CLA, DMA, and CPU Arbitration www.ti.com – CPU debug reads and writes The following accesses are ignored: – CPU.CLA1 writes Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 577: Cla Configuration And Debug
Map the data RAM to the CLA space by first, assigning ownership of the memory block to the CLA by writing a 1 to the memory block’s MemCfgRegs.LSxMSEL[MSEL_LSx] bit, and then specifying SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 578 If after some time you want to re-map these memories back to CPU space, then disable interrupts and make sure all tasks have completed by checking the MIRUN register. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 579: Debugging Cla Code
Enable the CLA breakpoints in the debugger. In Code Composer Studio, this is done by connecting to the CLA core (or tap) from the debug perspective. Breakpoints are disabled when the core is disconnected. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 580: Cla Illegal Opcode Behavior
CLA breakpoints are enabled or not. • The CLA will issue the task-specific interrupt to the PIE. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 581: Resetting The Cla
(MCTLBGRN.BGSTART) and Trigger Enable bit (MCTLBGRND.TRIGEN) are reset. The MVECTBGRNACTIVE is set to the value of MVECTBGRND, and the status register (MSTSBGRND) is also reset. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 582: Pipeline
The CLA does not have this protection mechanism. Instead the code must wait to perform the read. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 583: Write Followed By Read - Read Occurs First
These instructions must not be MSTOP, MDEBUGSTOP, MBCNDD, MCCNDD or MRCNDD. For a more detailed description refer to the functional description for MBCNDD, MCCNDD MRCNDD. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 584 – An MSTOP instruction is forced into the D2 phase of the pipeline; it will cause the background task Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 585: Adc To Cla Early Interrupt Response
ADC Activity CLA Activity Sample Sample Sample Conversion (1) Interrupt Received Conversion (2) Task Startup Conversion (3) Task Startup SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 586: Parallel Instructions
; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid) MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 587: Instruction Set
Flag value of 0 or 1 for selected flag (OR) 8 bit mask indicating the flag value; 0 or 1 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 588: Instruction Dest, Source1, Source2 Short Description
Each instruction has a table that gives a list of the operands and a short description. Instructions always have their destination operand(s) first followed by the source operand(s). Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 589: Addressing Modes And Encoding
Values not shown are reserved. Encoding for the shift fields in the MASR32, MLSR32 and MLSL32 instructions is shown in Table 4-9. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 590: Shift Field Encoding
This is the default operation if no CNDF field is specified. This condition will allow the ZF and NF flags to be modified when a conditional operation is executed. All other conditions will not modify these flags. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 591: Instructions
MMOV32 mem32, MRa — Move 32-Bit Floating-Point Register Contents to Memory ............MMOV32 mem32, MSTF — Move 32-Bit MSTF Register to Memory SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 592 MUI32TOF32 MRa, MRb — Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value ................MXOR32 MRa, MRb, MRc — Bitwise Exclusive Or Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 593 MMABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0 MNEGF32 MRa, MRb {, CNDF} See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 594 MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 595 MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 596 MMOV32 @_Result, MR1 ; Always executed MNOP ; Always executed MNOP ; Always executed MSTOP ; End of task Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 597 MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 598 MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 599: Maddf32 Mrd, Mre, Mrf||Mmov32 Mem32, Mra 32-Bit Floating-Point Addition With Parallel Move
MADDF32 MRa, MRb, MRc MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 600: Maddf32 Mrd, Mre, Mrf ||Mmov32 Mra, Mem32 32-Bit Floating-Point Addition With Parallel Move
; and in parallel store A+4B MMOV32 @Y2, MR3 ; store A + C MSTOP ; end of task Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 601 MADDF32 MRa, MRb, MRc MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 602: Mand32 Mra, Mrb, Mrc Bitwise And
MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 603: Masr32 Mra, #Shift - Arithmetic Shift Right
MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 604: Mbcndd 16Bitdest {, Cndf} - Branch Conditional Delayed
Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 605 ; d1 Can be any instruction <Destination 2> ; d2 <Destination 3> ; d3 ..MSTOP ..SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 606: Pipeline Activity For Mbcndd, Branch Not Taken
MBCNDD MBCNDD MBCNDD MBCNDD Table 4-14. Pipeline Activity For MBCNDD, Branch Taken Instruction MBCNDD MBCNDD MBCNDD MBCNDD MBCNDD Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 607 MOR32 MR3, MR2 ; Executed if (B) branch taken MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken MSTOP SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 608 Skip2: MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken MSTOP MCCNDD 16BitDest, CNDF See also MRCNDD CNDF Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 609: Mccndd 16Bitdest {, Cndf} - Call Conditional Delayed
MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details. This instruction does not modify flags in the MSTF register. Flags Flag Modified SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 610 – These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD, MCCNDD or MRCNDD. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 611 ; d9 Cannot be stop, branch, call or return <Destination 10> ; d10 Cannot be stop, branch, call or return <Destination 11> ; d11 ..MSTOP SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 612: Pipeline Activity For Mccndd, Call Not Taken
The RPC value in the MSTF register will point to the instruction following I7 (instruction I8). Example MBCNDD #16BitDest, CNDF See also MMOV32 mem32, MSTF MMOV32 MSTF, mem32 MRCNDD CNDF Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 613: Mclrc Bgintm - Clear Background Task Interrupt Mask
; Allow the background task to be ; interrupted by clearing the ; MSTSBGRND.BGINTM bit MSETC BGINTM See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 614 MCMP32 MR1, MR0 ; NF = 0, ZF = 0 MADD32 MRa, MRb, MRc See also MSUB32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 615: Mcmpf32 Mra, Mrb - 32-Bit Floating-Point Compare For Equal, Less Than Or Greater Than
; ZF = 1, NF = 0 MCMPF32 MRa, #16FHi See also MMAXF32 MRa, #16FHi MMAXF32 MRa, MRb MMINF32 MRa, #16FHi MMINF32 MRa, MRb SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 616: Mcmpf32 Mra, #16Fhi - 32-Bit Floating-Point Compare For Equal, Less Than Or Greater Than
MR0, #6.5 ; ZF = 0, NF = 1 MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 617 ; End of task MCMPF32 MRa, MRb See also MMAXF32 MRa, #16FHi MMAXF32 MRa, MRb MMINF32 MRa, #16FHi MMINF32 MRa, MRb SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 618: Mdebugstop - Debug Stop Task
This instruction does not modify flags in the MSTF register. Flags Flag Modified This is a single-cycle instruction. Pipeline Example MSTOP, MDEBUGSTOP1 See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 619: Mdebugstop1 - Software Breakpoint
This instruction does not modify flags in the MSTF register. Flags Flag Modified This is a single-cycle instruction. Pipeline Example MSTOP, MDEBUGSTOP See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 620: Meallow - Enable Cla Write Access To Eallow Protected Registers
; Allow CLA write access MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL MEDIS ; Disallow CLA write access MSTOP MEDIS See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 621: Medis - Disable Cla Write Access To Eallow Protected Registers
; Allow CLA write access MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL MEDIS ; Disallow CLA write access MSTOP MEALLOW See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 622: Meinvf32 Mra, Mrb - 32-Bit Floating-Point Reciprocal Approximation
; MR0 = Y = Ye*Num MMOV32 @_Dest, MR0 ; Store result MSTOP ; end of task MEISQRTF32 MRa, MRb See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 623: Meisqrtf32 Mra, Mrb - 32-Bit Floating-Point Square-Root Reciprocal Approximation
MMOV32 @_y, MR0 ; Store Y = sqrt(X) MSTOP ; end of task MEINVF32 MRa, MRb See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 624: Mf32Toi16 Mra, Mrb - Convert 32-Bit Floating-Point Value To 16-Bit Integer
MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 625: Mf32Toi16R Mra, Mrb - Convert 32-Bit Floating-Point Value To 16-Bit Integer And Round
MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 626 ; end of task MF32TOUI32 MRa, MRb See also MI32TOF32 MRa, MRb MI32TOF32 MRa, mem32 MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 627: Mf32Toui16 Mra, Mrb - Convert 32-Bit Floating-Point Value To 16-Bit Unsigned Integer
MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 628: Mf32Toui16R Mra, Mrb Convert 32-Bit Floating-Point Value To 16-Bit Unsigned Integer And Round
MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 629: Mf32Toui32 Mra, Mrb - Convert 32-Bit Floating-Point Value To 32-Bit Unsigned Integer
; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000) MF32TOI32 MRa, MRb See also MI32TOF32 MRa, MRb MI32TOF32 MRa, mem32 MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 630: Mfracf32 Mra, Mrb - Fractional Portion Of A 32-Bit Floating-Point Value
MR2, #19.625 ; MR2 = 19.625 (0x419D0000) MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0) See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 631: Mi16Tof32 Mra, Mrb - Convert 16-Bit Integer To 32-Bit Floating-Point Value
MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 632 MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 633 ; end of task MF32TOI32 MRa, MRb See also MF32TOUI32 MRa, MRb MI32TOF32 MRa, MRb MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 634 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888) MF32TOI32 MRa, MRb See also MF32TOUI32 MRa, MRb MI32TOF32 MRa, mem32 MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 635 MAND32 MRa, MRb, MRc MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 636 MAND32 MRa, MRb, MRc MLSL32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 637 == 0) { ZF = 1; NF = 0; } MMACF32 and MMOV32 complete in a single cycle. Pipeline SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 638 ; MR3 = (A + B + C + D) + E MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 639 ; Y1 = MR3 MSTOP ; end of task MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 640 @_Result, MR1 ; Always executed MNOP ; Always executed MNOP ; Always executed MSTOP ; End of task Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 641 MCMPF32 MRa, MRb See also MCMPF32 MRa, #16FHi MMAXF32 MRa, #16FHi MMINF32 MRa, MRb MMINF32 MRa, #16FHi SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 642 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0 MMAXF32 MRa, MRb See also MMINF32 MRa, MRb MMINF32 MRa, #16FHi Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 643 @_Result, MR1 ; Always executed MNOP ; Always executed MNOP ; Always executed MSTOP ; End of task SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 644 Instruction Set www.ti.com MMAXF32 MRa, MRb See also MMAXF32 MRa, #16FHi MMINF32 MRa, #16FHi Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 645 ; MR2 = -1.5, ZF = 1, NF = 0 MMAXF32 MRa, #16FHi See also MMAXF32 MRa, MRb MMINF32 MRa, MRb SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 646: Pipeline Activity For Mmov16 Marx, Mra , #16I
Table 4-17. Pipeline Activity For MMOV16 MARx, MRa , #16I Instruction MMOV16 MAR0, MR0, #_X MMOV16 MMOV16 MMOV16 MMOV16 MMOV16 MMOV16 MMOV1 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 647 ; Always executed: MR1=0 MNOP MNOP MMOV16 @_ConversionCount, MR0 ; If branch not taken MSTOP ; store current count SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 648 ; This task initializes the ConversionCount ; to zero _Cla1Task8: MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _ClaT8End: See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 649: Pipeline Activity For Mmov16 Mar0/Mar1, Mem16
Table 4-18. Pipeline Activity For MMOV16 MAR0/MAR1, mem16 Instruction MMOV16 MAR0, @_X MMOV16 MMOV16 MMOV16 MMOV16 MMOV16 MMOV16 MMOV1 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 650 ; This task initializes the ConversionCount ; to zero _Cla1Task8: MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _ClaT8End: See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 651 No flags MSTF flags are affected. Flags Flag Modified This is a single-cycle instruction. Pipeline Example See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 652 ; Always executed: MR1=0 MNOP MNOP MMOV16 @_ConversionCount, MR0 ; If branch not taken MSTOP ; store current count Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 653 ; to zero _Cla1Task8: MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _ClaT8End: MMOVIZ MRa, #16FHi See also MMOVXI MRa, #16FLoHex SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 654 ; MR3 = (A + B + C + D) + E MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task MMOV32 mem32, MSTF See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 655 This instruction does not modify flags in the MSTF register: Flags Flag Modified This is a single-cycle instruction. Pipeline Example MMOV32 mem32, MRa See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 656: Mmov32 Mra, Mem32 {, Cndf} - Conditional 32-Bit Move
== 0) { ZF = 1; NF = 0; } else No flags modified; This is a single-cycle instruction. Pipeline Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 657 ; Store Y MSTOP ; end of task MMOV32 MRa, MRb {, CNDF} See also MMOVD32 MRa, mem32 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 658: Mmov32 Mra, Mrb {, Cndf} - Conditional 32-Bit Move
== 0) {ZF = 1; NF = 0;} else No flags modified; This is a single-cycle instruction. Pipeline Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 659 ; true, MR2 = MR1 = 2.0 MMOV32 MR2, MR0, LT ; false, does not load MR2 MSTOP MMOV32 MRa, mem32 {,CNDF} See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 660: Mmov32 Mstf, Mem32 - Move 32-Bit Value From Memory To The Mstf Register
Loading the status register will overwrite all flags and the RPC field. The MEALLOW field is not affected. This is a single-cycle instruction. Pipeline Example MMOV32 mem32, MSTF See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 661: Mmovd32 Mra, Mem32 - Move 32-Bit Value From Memory With Data Copy
MMOV32 @_Y1, MR3 ; Y1 = MR3 MSTOP ; end of task MMOV32 MRa, mem32 {,CNDF} See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 662: Mmovf32 Mra, #32F - Load The 32-Bits Of A 32-Bit Floating-Point Register
; MMOVIZ MR3, #0x4144 ; MMOVXI MR3, #0x3D71 MMOVIZ MRa, #16FHi See also MMOVXI MRa, #16FLoHex MMOVI32 MRa, #32FHex Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 663: Mmovi16 Marx, #16I - Load The Auxiliary Register With The 16-Bit Immediate Value
Table 4-19. Pipeline Activity For MMOVI16 MAR0/MAR1, #16I Instruction MMOVI16 MAR0, #_X MMOVI16 MMOVI16 MMOVI16 MMOVI16 MMOVI16 MMOVI16 MMOVI SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 664: Mmovi32 Mra, #32Fhex - Load The 32-Bits Of A 32-Bit Floating-Point Register With The Immediate
; MMOVIZ MR0, #0x0000 ; MMOVXI MR0, #0x4040 MMOVIZ MRa, #16FHi See also MMOVXI MRa, #16FLoHex MMOVF32 MRa, #32F Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 665: Mmoviz Mra, #16Fhi - Load The Upper 16-Bits Of A 32-Bit Floating-Point Register
MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB MMOVF32 MRa, #32F See also MMOVI32 MRa, #32FHex MMOVXI MRa, #16FLoHex SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 666: Mmovz16 Mra, Mem16 - Load Mrx With 16-Bit Value
The MSTF register flags are modified based on the integer results of the operation. NF = 0; if (MRa(31:0)== 0) { ZF = 1; } This is a single-cycle instruction. Pipeline Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 667: Mmovxi Mra, #16Flohex - Move Immediate To The Low 16-Bits Of A Floating-Point Register
; Load MR0 with pi = 3.141593 (0x40490FDB) MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000 MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB MMOVIZ MRa, #16FHi See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 668: Mmpyf32 Mra, Mrb, Mrc 32-Bit Floating-Point Multiply
MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 669: Mmpyf32 Mra, #16Fhi, Mrb 32-Bit Floating-Point Multiply
MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000) MMOV32 @_X, MR0 ; Save the result in variable X SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 670 MMPYF32 MRa, MRb, #16FHi See also MMPYF32 MRa, MRb, MRc MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 671: Mmpyf32 Mra, Mrb, #16Fhi - 32-Bit Floating-Point Multiply
; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000) MMOV32 @_X, MR0 ; Save the result in variable X SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 672 ; store result MSTOP ; end of task MMPYF32 MRa, #16FHi, MRb See also MMPYF32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 673 LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition. Both MMPYF32 and MADDF32 complete in a single cycle. Pipeline SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 674 ; Store the result MSTOP ; end of task MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 675: Mmpyf32 Mrd, Mre, Mrf ||Mmov32 Mra, Mem32 - 32-Bit Floating-Point Multiply With Parallel Move
; Add M*X1 to B1 and store in MR1 MMOV32 @Y1, MR1 ; Store the result MSTOP ; end of task SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 676 MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa See also MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 677: Mmpyf32 Mrd, Mre, Mrf ||Mmov32 Mem32, Mra - 32-Bit Floating-Point Multiply With Parallel Move
MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32 See also MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 678 See also MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 679: Mnegf32 Mra, Mrb{, Cndf} Conditional Negation
MR0, MR1 ; NF = 0 MNEGF32 MR0, MR0, GEQ ; if NF = 0, MR0 = -20.0 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 680 ; MR0 = Y = Ye*Num MMOV32 @_Dest, MR0 ; Store result MSTOP ; end of task MABSF32 MRa, MRb See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 681: Mnop - No Operation
; Pad to seperate MBCNDD and MSTOP MNOP ; Pad to seperate MBCNDD and MSTOP MSTOP ; End of task See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 682: Mor32 Mra, Mrb, Mrc - Bitwise Or
MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE MAND32 MRa, MRb, MRc See also MXOR32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 683: Mrcndd {Cndf} - Return Conditional Delayed
All other conditions will not modify these flags. This instruction does not modify flags in the MSTF register. Flags Flag Modified SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 684 – The three instructions proceeding MRCNDD can change MSTF flags but will have no effect on whether the MRCNDD instruction makes the return or not. This is Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 685: Pipeline Activity For Mrcndd, Return Not Taken
Table 4-21. Pipeline Activity For MRCNDD, Return Taken Instruction MRCNDD MRCNDD MRCNDD MRCNDD MRCNDD etc......SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 686 Instruction Set www.ti.com Example MBCNDD #16BitDest, CNDF See also MCCNDD 16BitDest, CNDF MMOV32 mem32, MSTF MMOV32 MSTF, mem32 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 687: Msetc Bgintm - Set Background Task Interrupt Mask
; Set the MSTSBGRND.BGINTM bit ; to prevent any other tasks from ; interrupting the background task MCLRC BGINTM See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 688: Msetflg Flag, Value - Set Or Clear Selected Floating-Point Status Flags
MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX; MMOV32 mem32, MSTF See also MMOV32 MSTF, mem32 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 689: Mstop Stop Task
MSTOP Pipeline instruction. The MSTOP instruction cannot be placed with 3 instructions of a MBCNDD, MCCNDD MRCNDD instruction. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 690: Pipeline Activity For Mstop
MR3, MR3, MR2 ; A + B + C = 6 (0x0000006) MMOV32 @_y2, MR3 ; Store y2 MSTOP ; End of task MDEBUGSTOP MDEBUGSTOP1 See also Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 691: Msub32 Mra, Mrb, Mrc - 32-Bit Integer Subtraction
MAND32 MRa, MRb, MRc MASR32 MRa, #SHIFT MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 692: Msubf32 Mra, Mrb, Mrc 32-Bit Floating-Point Subtraction
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 693: Msubf32 Mra, #16Fhi, Mrb 32-Bit Floating-Point Subtraction
MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 694 MSUBF32 MRa, MRb, MRc See also MSUBF32 MRa, #16FHi, MRb MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 695 MSUBF32 MRa, #16FHi, MRb MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 696 This instruction modifies the following flags in the MSTF register: Flags Flag Modified No flags affected This is a single-cycle instruction. Pipeline Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 697 ; Always executed MNOP ; Always executed MNOP ; Always executed MSTOP ; End of task See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 698: Mtesttf Cndf Test Mstf Register Flag Condition
Note: If (CNDF == UNC or UNCF), the TF flag will be set to 1. This is a single-cycle instruction. Pipeline Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 699 ; end of task if (B) branch not taken _Skip2: MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken MSTOP See also SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 700 MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 701 MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 702 ; end of task MF32TOI32 MRa, MRb See also MF32TOUI32 MRa, MRb MI32TOF32 MRa, mem32 MI32TOF32 MRa, MRb MUI32TOF32 MRa, MRb Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 703 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011) MF32TOI32 MRa, MRb See also MF32TOUI32 MRa, MRb MI32TOF32 MRa, mem32 MI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 704 MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476 MAND32 MRa, MRb, MRc See also MOR32 MRa, MRb, MRc Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 705: Registers
Register Name Start Address End Address Cla1OnlyRegs CLA_ONLY_REGS 0x0000_0C00 0x0000_0CFF Cla1SoftIntRegs CLA_SOFTINT_REGS 0x0000_0CE0 0x0000_0CFF Cla1Regs CLA_REGS 0x0000_1400 0x0000_147F SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 706: Cla_Only_Regs Registers
Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 707: Mvectbgrndactive Register
Gives the current interrupted MPC value of the background task, if the background task was running and interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 708: Mpsactl Register
1 PSA1 calculated on every bus event MPABSTART CLA Program Address Bus PSA1 Start/Stop Bit: 0 PSA1 stopped 1 PSA1 start Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 709: Mpsa1 Register
Register value is cleared to zero by reset or by writing to the MPSA1CLEAR bit in the MPSACTL register. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 710: Mpsa2 Register
Register value is cleared to zero by reset or by writing to the MPSA2CLEAR bit in the MPSACTL register. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 711: Softinten Register
CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 712: Softintfrc Register
Write of '1' will generate a CLA software interrupt to the CPU for the corresponding task. Write of '0' has no effect. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 713: Cla_Regs Registers
Table 4-33. CLA_REGS Access Type Codes Access Type Code Description Read Type Read Read Write Type Write SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 714 Code Description Write 1 to clear Write Reset or Default Value Value after reset or the default value Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 715: Mvect1 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 716: Mvect2 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 717: Mvect3 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 718: Mvect4 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 719: Mvect5 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 720: Mvect6 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 721: Mvect7 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 722: Mvect8 Register
MVECT1, interrupt 2 uses MVECT2 and so forth. Note: While the CLA is running or executing a task, the CPU can change the MVECT values.. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 723: Mctl Register
1h (R/W) = Writing a 1 will cause a hard reset of the CLA. This will set all CLA registers to their default state. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 724: Mvectbgrndactive Register
Gives the current interrupted MPC value of the background task, if the background task was running and interrupted, or reflects the MVECTBGRND value, if MCTLBGRND.BGSTART bit is 0. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 725: Softinten Register
CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 726: Mstsbgrnd Register
Value of 1 indicates that background task is running. Value of 0 indicates that background task is not running. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 727: Mctlbgrnd Register
- If the background task is running and this bit is cleared, it will not have any effect on the task execution. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 728: Mvectbgrnd Register
. The value in this register is forced into the MPC register, when the background task starts. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 729: Mifr Register
Task 8 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 8 interrupt has been received and is pending execution SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 730 Task 5 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 5 interrupt has been received and is pending execution Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 731 Task 2 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 2 interrupt has been received and is pending execution SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 732 Task 1 interrupt is currently not flagged (default) 1h (R/W) = TASK_FLAG_ENABLE Task 1 interrupt has been received and is pending execution Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 733: Miovf Register
0h (R/W) = A task 7 interrupt overflow has not occurred (default) 1h (R/W) = A task 7 interrupt overflow has occurred SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 734 0h (R/W) = A task 3 interrupt overflow has not occurred (default) 1h (R/W) = A task 3 interrupt overflow has occurred Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 735 0h (R/W) = A task 1 interrupt overflow has not occurred (default) 1h (R/W) = A task 1 interrupt overflow has occurred SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 736: Mifrc Register
0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 4 interrupt Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 737 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to force the task 1 interrupt SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 738: Miclr Register
0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 4 interrupt flag Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 739 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 1 interrupt flag SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 740: Miclrovf Register
0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 4 interrupt overflow flag Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 741 0h (R/W) = This bit always reads back 0 and writes of 0 have no effect 1h (R/W) = Write a 1 to clear the task 1 interrupt overflow flag SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 742: Mier Register
0h (R/W) = TASK_INT_DISABLE Task 7 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 7 interrupt is enabled Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 743 0h (R/W) = TASK_INT_DISABLE Task 3 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 3 interrupt is enabled SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 744 0h (R/W) = TASK_INT_DISABLE Task 1 interrupt is disabled (default) 1h (R/W) = TASK_INT_ENABLE Task 1 interrupt is enabled Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 745: Mirun Register
0h (R/W) = Task 6 is not executing (default) 1h (R/W) = Task 6 is executing SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 746 0h (R/W) = Task 1 is not executing (default) 1h (R/W) = Task 1 is executing Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 747: Mpc Register
[2] After a STOP operation, and with no other task pending, the PC will remain pointing to the STOP operation. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 748: Mar0 Register
_MAR0 R-0h Table 4-56. _MAR0 Register Field Descriptions Field Type Reset Description 15-0 _MAR0 CLA Auxillary Register 0 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 749: Mar1 Register
_MAR1 R-0h Table 4-57. _MAR1 Register Field Descriptions Field Type Reset Description 15-0 _MAR1 CLA Auxillary Register 1 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 750: Mstf Register
1h (R/W) = If this bit is one, the MMPYF32, MADDF32 and MSUBF32 instructions will round to the nearest even value. RESERVED Reserved Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 751 0h (R/W) = An underflow condition has not been latched 1h (R/W) = An underflow condition has been latched SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 752 0h (R/W) = An overflow condition has not been latched 1h (R/W) = An overflow condition has been latched Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 753: Mr0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R-0h Table 4-59. _MR0 Register Field Descriptions Field Type Reset Description 31-0 CLA Result Register 0 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 754: Mr1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R-0h Table 4-60. _MR1 Register Field Descriptions Field Type Reset Description 31-0 CLA Result Register 1 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 755: Mr2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R-0h Table 4-61. _MR2 Register Field Descriptions Field Type Reset Description 31-0 CLA Result Register 2 SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 756: Mr3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R-0h Table 4-62. _MR3 Register Field Descriptions Field Type Reset Description 31-0 CLA Result Register 3 Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 757: Mpsactl Register
1 PSA1 calculated on every bus event MPABSTART CLA Program Address Bus PSA1 Start/Stop Bit: 0 PSA1 stopped 1 PSA1 start SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 758: Mpsa1 Register
Register value is cleared to zero by reset or by writing to the MPSA1CLEAR bit in the MPSACTL register. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 759: Mpsa2 Register
Register value is cleared to zero by reset or by writing to the MPSA2CLEAR bit in the MPSACTL register. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 760: Cla_Softint_Regs Registers
Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 761: Softinten Register
CPU in this case. Note: SOFTINTEN register is read only in the CPU memory map. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 762: Softintfrc Register
Write of '1' will generate a CLA software interrupt to the CPU for the corresponding task. Write of '0' has no effect. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 763: Cla_Prom_Crc32_Regs Registers
Read Type Read Read Write Type Write Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 764: Crc32_Controlreg Register
1: will start the CRC calulations Notes: Setting this anytime during the CRC caluclation will reset and re-start the CRC calulation. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 765: Crc32_Startaddress Register
Type Reset Description 31-0 START_ADDRESS START_ADDRESS defines starting point for CRC32 calculation. Note that it is CLA address SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 766: Crc32_Seed Register
Initial value of CRC, this value is coiped to the CRC register on triggering CRC calculation by writing to START bit. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 767: Crc32_Statusreg Register
CURRENTADDR The current address of data fetch unit - this is 32 bit aligned offset address of ROM SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 768: Crc32_Crcresult Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CRCRESULT R-0h Table 4-76. CRC32_CRCRESULT Register Field Descriptions Field Type Reset Description 31-0 CRCRESULT CRC result register Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 769: Crc32_Goldencrc Register
After the CRC is done, GOLDENCRC will be compared with CRCRESULT and the CRCCHECKSTATUS bit will be updated. SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 770: Crc32_Inten Register
Field Type Reset Description 31-2 RESERVED Reserved CRCDONE 0 CRCDONE Interrupt disabled 1 CRCDONE Interrupt enabled RESERVED Reserved Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 771: Crc32_Flg Register
0 CRC calulation is in progress or CRC module is idle. 1 CRC calulation is done. Global Interrupt Status flag 0 No interrupt generated 1 Interrupt was generated SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 772: Crc32_Clr Register
1 Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1. Control Law Accelerator (CLA) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 773: Crc32_Frc Register
RESERVED Reserved CRCDONE R=0/W=1 Force CRCDONE interrupt flag 0 No effect 1 Force CRCDONE interrupt flag RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 Control Law Accelerator (CLA) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 774: Cla Program Rom (Clapromcrc)
The CLAPROMCRC is a feature which calculates a CRC-32 value of a configurable block of data in the CLA program ROM space..........................Topic Page ......................Overview ..................Functional Description CLA Program ROM (CLAPROMCRC) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 775 The seed is the initial value used for the CRC-32 calculation. Therefore, the result will vary with the initial seed. The seed can be written into the CRC32_SEED register. SPRUI33 – November 4 2015 – Revised January 2017 CLA Program ROM (CLAPROMCRC) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 776: Halt
CRC will be compared with the final result and the module will then set a pass or fail bit accordingly in the status register (CRC32_STATUSREG). CLA Program ROM (CLAPROMCRC) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 777: General-Purpose Input/Output (Gpio)
Digital General-Purpose I/O Control .................... Input Qualification ................GPIO and Peripheral Muxing ............Internal Pull-up Configuration Requirements ......................Registers SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 778: Gpio Overview
Likewise, external interrupts can be generated from peripheral activity. All pin options (such as input qualification and pull-ups) are valid for all masters and peripherals. General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 779: Configuration Overview
Once the GPIOs are configured, they can be individually assigned to the CLA via the GPyCSEL1-4 registers. Assigning an output pin to the CLA causes the CLA's GPySET, GPyCLEAR, GPyTOGGLE, SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 780: Digital General-Purpose I/O Control
NOTE: Using input synchronization when the peripheral itself performs the synchronization may cause unexpected results. The user should ensure that the GPIO pin is configured for asynchronous in this case. General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 781: Synchronization To Sysclk Only
If GPyCTRL[QUALPRDn] ≠ 0 × 1 ÷ (2 × GPyCTRL[QUALPRDn]) SYSCLK Where f is the frequency of SYSCLK SYSCLK SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 782: Case 1: Three-Sample Sampling Window Width
If GPyCTRL[QUALPRDn] ≠ 0 5 × 2 × GPyCTRL[QUALPRDn] × T SYSCLK Where T is the period in time of SYSCLK SYSCLK General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 783: Input Qualifier Clock Cycles
(5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 784: Gpio And Peripheral Muxing
Input mode and driven on the board by another component to a level above V or below V • Input mode with GPIO internal pull-up enabled • Output mode General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 785 GPIOs for the package they are using. Users should take care to avoid disabling these pull-ups in their application code. SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 786: Registers
Table 6-7. GPIO Base Address Table Device Registers Register Name Start Address End Address GpioCtrlRegs GPIO_CTRL_REGS 0x0000_7C00 0x0000_7EFF GpioDataRegs GPIO_DATA_REGS 0x0000_7F00 0x0000_7FFF General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 787: Gpio_Ctrl_Regs Registers
GPIO B Master Core Select (GPIO48 to EALLOW GPIO55) GPBCSEL4 GPIO B Master Core Select (GPIO56 to EALLOW GPIO63) SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 788: Gpio_Ctrl_Regs Access Type Codes
Write Type Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 789: Gpactrl Register
Qualification sampling period for GPIO16 to GPIO23 15-8 QUALPRD1 Qualification sampling period for GPIO8 to GPIO15 QUALPRD0 Qualification sampling period for GPIO0 to GPIO7 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 790: Gpaqsel1 Register
Input qualification type for GPIO3 GPIO2 Input qualification type for GPIO2 GPIO1 Input qualification type for GPIO1 GPIO0 Input qualification type for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 791: Gpaqsel2 Register
Input qualification type for GPIO19 GPIO18 Input qualification type for GPIO18 GPIO17 Input qualification type for GPIO17 GPIO16 Input qualification type for GPIO16 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 792: Gpamux1 Register
Lower 2 bits of peripheral mux configuration for GPIO1 GPIO0 Lower 2 bits of peripheral mux configuration for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 793: Gpamux2 Register
Lower 2 bits of peripheral mux configuration for GPIO17 GPIO16 Lower 2 bits of peripheral mux configuration for GPIO16 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 794: Gpadir Register
Data direction for GPIO14 GPIO13 Data direction for GPIO13 GPIO12 Data direction for GPIO12 GPIO11 Data direction for GPIO11 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 795 Data direction for GPIO3 GPIO2 Data direction for GPIO2 GPIO1 Data direction for GPIO1 GPIO0 Data direction for GPIO0 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 796: Gpapud Register
Pull-up disable for GPIO13 GPIO12 Pull-up disable for GPIO12 GPIO11 Pull-up disable for GPIO11 GPIO10 Pull-up disable for GPIO10 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 797 Pull-up disable for GPIO3 GPIO2 Pull-up disable for GPIO2 GPIO1 Pull-up disable for GPIO1 GPIO0 Pull-up disable for GPIO0 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 798: Gpainv Register
Input inversion for GPIO13 GPIO12 Input inversion for GPIO12 GPIO11 Input inversion for GPIO11 GPIO10 Input inversion for GPIO10 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 799 Input inversion for GPIO3 GPIO2 Input inversion for GPIO2 GPIO1 Input inversion for GPIO1 GPIO0 Input inversion for GPIO0 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 800: Gpaodr Register
Open-drain output mode for GPIO15 GPIO14 Open-drain output mode for GPIO14 GPIO13 Open-drain output mode for GPIO13 GPIO12 Open-drain output mode for GPIO12 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 801 Open-drain output mode for GPIO3 GPIO2 Open-drain output mode for GPIO2 GPIO1 Open-drain output mode for GPIO1 GPIO0 Open-drain output mode for GPIO0 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 802: Gpaamsel Register
Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 803 Table 6-19. GPAAMSEL Register Field Descriptions (continued) Field Type Reset Description RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 804: Gpagmux1 Register
Upper 2 bits of peripheral mux configuration for GPIO1 GPIO0 Upper 2 bits of peripheral mux configuration for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 805: Gpagmux2 Register
Upper 2 bits of peripheral mux configuration for GPIO17 GPIO16 Upper 2 bits of peripheral mux configuration for GPIO16 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 806: Gpacsel1 Register
11-8 GPIO2 Master core select for GPIO2 GPIO1 Master core select for GPIO1 GPIO0 Master core select for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 807: Gpacsel2 Register
11-8 GPIO10 Master core select for GPIO10 GPIO9 Master core select for GPIO9 GPIO8 Master core select for GPIO8 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 808: Gpacsel3 Register
11-8 GPIO18 Master core select for GPIO18 GPIO17 Master core select for GPIO17 GPIO16 Master core select for GPIO16 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 809: Gpacsel4 Register
11-8 GPIO26 Master core select for GPIO26 GPIO25 Master core select for GPIO25 GPIO24 Master core select for GPIO24 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 810: Gpalock Register
Configuration lock for GPIO14 GPIO13 Configuration lock for GPIO13 GPIO12 Configuration lock for GPIO12 GPIO11 Configuration lock for GPIO11 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 811 Configuration lock for GPIO3 GPIO2 Configuration lock for GPIO2 GPIO1 Configuration lock for GPIO1 GPIO0 Configuration lock for GPIO0 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 812: Gpacr Register
Configuration lock commit for GPIO13 GPIO12 R/WSOnce Configuration lock commit for GPIO12 GPIO11 R/WSOnce Configuration lock commit for GPIO11 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 813 Configuration lock commit for GPIO2 GPIO1 R/WSOnce Configuration lock commit for GPIO1 GPIO0 R/WSOnce Configuration lock commit for GPIO0 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 814: Gpbctrl Register
Qualification sampling period for GPIO48 to GPIO55 15-8 QUALPRD1 Qualification sampling period for GPIO40 to GPIO47 QUALPRD0 Qualification sampling period for GPIO32 to GPIO39 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 815: Gpbqsel1 Register
Input qualification type for GPIO35 GPIO34 Input qualification type for GPIO34 GPIO33 Input qualification type for GPIO33 GPIO32 Input qualification type for GPIO32 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 816: Gpbqsel2 Register
Input qualification type for GPIO51 GPIO50 Input qualification type for GPIO50 GPIO49 Input qualification type for GPIO49 GPIO48 Input qualification type for GPIO48 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 817: Gpbmux1 Register
Lower 2 bits of peripheral mux configuration for GPIO33 GPIO32 Lower 2 bits of peripheral mux configuration for GPIO32 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 818: Gpbmux2 Register
Lower 2 bits of peripheral mux configuration for GPIO49 GPIO48 Lower 2 bits of peripheral mux configuration for GPIO48 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 819: Gpbdir Register
Data direction for GPIO46 GPIO45 Data direction for GPIO45 GPIO44 Data direction for GPIO44 GPIO43 Data direction for GPIO43 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 820 Data direction for GPIO35 GPIO34 Data direction for GPIO34 GPIO33 Data direction for GPIO33 GPIO32 Data direction for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 821: Gpbpud Register
Pull-up disable for GPIO45 GPIO44 Pull-up disable for GPIO44 GPIO43 Pull-up disable for GPIO43 GPIO42 Pull-up disable for GPIO42 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 822 Pull-up disable for GPIO35 GPIO34 Pull-up disable for GPIO34 GPIO33 Pull-up disable for GPIO33 GPIO32 Pull-up disable for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 823: Gpbinv Register
Input inversion for GPIO45 GPIO44 Input inversion for GPIO44 GPIO43 Input inversion for GPIO43 GPIO42 Input inversion for GPIO42 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 824 Input inversion for GPIO35 GPIO34 Input inversion for GPIO34 GPIO33 Input inversion for GPIO33 GPIO32 Input inversion for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 825: Gpbodr Register
Open-drain output mode for GPIO46 GPIO45 Open-drain output mode for GPIO45 GPIO44 Open-drain output mode for GPIO44 GPIO43 Open-drain output mode for GPIO43 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 826 Open-drain output mode for GPIO35 GPIO34 Open-drain output mode for GPIO34 GPIO33 Open-drain output mode for GPIO33 GPIO32 Open-drain output mode for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 827: Gpbgmux1 Register
Upper 2 bits of peripheral mux configuration for GPIO33 GPIO32 Upper 2 bits of peripheral mux configuration for GPIO32 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 828: Gpbgmux2 Register
Upper 2 bits of peripheral mux configuration for GPIO49 GPIO48 Upper 2 bits of peripheral mux configuration for GPIO48 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 829: Gpbcsel1 Register
11-8 GPIO34 Master core select for GPIO34 GPIO33 Master core select for GPIO33 GPIO32 Master core select for GPIO32 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 830: Gpbcsel2 Register
11-8 GPIO42 Master core select for GPIO42 GPIO41 Master core select for GPIO41 GPIO40 Master core select for GPIO40 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 831: Gpbcsel3 Register
11-8 GPIO50 Master core select for GPIO50 GPIO49 Master core select for GPIO49 GPIO48 Master core select for GPIO48 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 832: Gpbcsel4 Register
11-8 GPIO58 Master core select for GPIO58 GPIO57 Master core select for GPIO57 GPIO56 Master core select for GPIO56 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 833: Gpblock Register
Configuration lock for GPIO46 GPIO45 Configuration lock for GPIO45 GPIO44 Configuration lock for GPIO44 GPIO43 Configuration lock for GPIO43 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 834 Configuration lock for GPIO35 GPIO34 Configuration lock for GPIO34 GPIO33 Configuration lock for GPIO33 GPIO32 Configuration lock for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 835: Gpbcr Register
Configuration lock commit for GPIO45 GPIO44 R/WSOnce Configuration lock commit for GPIO44 GPIO43 R/WSOnce Configuration lock commit for GPIO43 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 836 Configuration lock commit for GPIO34 GPIO33 R/WSOnce Configuration lock commit for GPIO33 GPIO32 R/WSOnce Configuration lock commit for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 837: Gphctrl Register
Qualification sampling period for GPIO240 to GPIO247 15-8 QUALPRD1 Qualification sampling period for GPIO232 to GPIO239 QUALPRD0 Qualification sampling period for GPIO224 to GPIO231 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 838: Gphqsel1 Register
Input qualification type for GPIO227 GPIO226 Input qualification type for GPIO226 GPIO225 Input qualification type for GPIO225 GPIO224 Input qualification type for GPIO224 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 839: Gphqsel2 Register
Input qualification type for GPIO243 GPIO242 Input qualification type for GPIO242 GPIO241 Input qualification type for GPIO241 GPIO240 Input qualification type for GPIO240 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 840: Gphinv Register
Input inversion for GPIO236 GPIO235 Input inversion for GPIO235 GPIO234 Input inversion for GPIO234 GPIO233 Input inversion for GPIO233 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 841 Input inversion for GPIO227 GPIO226 Input inversion for GPIO226 GPIO225 Input inversion for GPIO225 GPIO224 Input inversion for GPIO224 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 842: Gphamsel Register
Analog mode select for GPIO236 GPIO235 Analog mode select for GPIO235 GPIO234 Analog mode select for GPIO234 GPIO233 Analog mode select for GPIO233 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 843 Analog mode select for GPIO227 GPIO226 Analog mode select for GPIO226 GPIO225 Analog mode select for GPIO225 GPIO224 Analog mode select for GPIO224 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 844: Gphlock Register
Configuration lock for GPIO237 GPIO236 Configuration lock for GPIO236 GPIO235 Configuration lock for GPIO235 GPIO234 Configuration lock for GPIO234 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 845 Configuration lock for GPIO227 GPIO226 Configuration lock for GPIO226 GPIO225 Configuration lock for GPIO225 GPIO224 Configuration lock for GPIO224 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 846: Gphcr Register
Configuration lock commit for GPIO236 GPIO235 R/WSOnce Configuration lock commit for GPIO235 GPIO234 R/WSOnce Configuration lock commit for GPIO234 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 847 Configuration lock commit for GPIO226 GPIO225 R/WSOnce Configuration lock commit for GPIO225 GPIO224 R/WSOnce Configuration lock commit for GPIO224 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 848: Gpio_Data_Regs Registers
Code Description Read Type Read Write Type Write Reset or Default Value Value after reset or the default value General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 849: Gpadat Register
Read: Input value, Write: Output latch for GPIO18 GPIO17 Read: Input value, Write: Output latch for GPIO17 GPIO16 Read: Input value, Write: Output latch for GPIO16 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 850 Read: Input value, Write: Output latch for GPIO2 GPIO1 Read: Input value, Write: Output latch for GPIO1 GPIO0 Read: Input value, Write: Output latch for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 851: Gpaset Register
Output set for GPIO13 GPIO12 Output set for GPIO12 GPIO11 Output set for GPIO11 GPIO10 Output set for GPIO10 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 852 Output set for GPIO3 GPIO2 Output set for GPIO2 GPIO1 Output set for GPIO1 GPIO0 Output set for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 853: Gpaclear Register
Output clear for GPIO13 GPIO12 Output clear for GPIO12 GPIO11 Output clear for GPIO11 GPIO10 Output clear for GPIO10 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 854 Output clear for GPIO3 GPIO2 Output clear for GPIO2 GPIO1 Output clear for GPIO1 GPIO0 Output clear for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 855: Gpatoggle Register
Output toggle for GPIO13 GPIO12 Output toggle for GPIO12 GPIO11 Output toggle for GPIO11 GPIO10 Output toggle for GPIO10 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 856 Output toggle for GPIO3 GPIO2 Output toggle for GPIO2 GPIO1 Output toggle for GPIO1 GPIO0 Output toggle for GPIO0 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 857: Gpbdat Register
Read: Input value, Write: Output latch for GPIO49 GPIO48 Read: Input value, Write: Output latch for GPIO48 GPIO47 Read: Input value, Write: Output latch for GPIO47 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 858 Read: Input value, Write: Output latch for GPIO34 GPIO33 Read: Input value, Write: Output latch for GPIO33 GPIO32 Read: Input value, Write: Output latch for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 859: Gpbset Register
Output set for GPIO44 GPIO43 Output set for GPIO43 GPIO42 Output set for GPIO42 GPIO41 Output set for GPIO41 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 860 Output set for GPIO35 GPIO34 Output set for GPIO34 GPIO33 Output set for GPIO33 GPIO32 Output set for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 861: Gpbclear Register
Output clear for GPIO44 GPIO43 Output clear for GPIO43 GPIO42 Output clear for GPIO42 GPIO41 Output clear for GPIO41 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 862 Output clear for GPIO35 GPIO34 Output clear for GPIO34 GPIO33 Output clear for GPIO33 GPIO32 Output clear for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 863: Gpbtoggle Register
Output toggle for GPIO44 GPIO43 Output toggle for GPIO43 GPIO42 Output toggle for GPIO42 GPIO41 Output toggle for GPIO41 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 864 Output toggle for GPIO35 GPIO34 Output toggle for GPIO34 GPIO33 Output toggle for GPIO33 GPIO32 Output toggle for GPIO32 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 865: Gphdat Register
Read: Input value for GPIO235 GPIO234 Read: Input value for GPIO234 GPIO233 Read: Input value for GPIO233 GPIO232 Read: Input value for GPIO232 SPRUI33 – November 4 2015 – Revised January 2017 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 866 Read: Input value for GPIO227 GPIO226 Read: Input value for GPIO226 GPIO225 Read: Input value for GPIO225 GPIO224 Read: Input value for GPIO224 General-Purpose Input/Output (GPIO) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 867: Crossbar (X-Bar)
You can read more about each of these X-BARs in the following sections..........................Topic Page .................... GPIO Input X-BAR ................ePWM and GPIO Output X-BAR ....................X-BAR Registers SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 868: Gpio Input X-Bar
X-BAR TRIP10 TRIP11 TRIP12 Other Sources ADCEXTSOC EXTSYNCIN1 ePWM and eCAP Sync Chain EXTSYNCIN2 Other Sources Other Sources Output X-BAR Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 869: Epwm And Gpio Output X-Bar
SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 870: Epwm Architecture - Single Output
OR’d before being passed on to the respective TRIPx signal on the ePWM. You may also optionally invert the signal via the TRIPOUTINV register. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 871: Epwm X-Bar Mux Configuration Table
SD1FLT1.COMPH SD1FLT1.COMPH_OR_COMPL SD1FLT1.COMPL INPUT7 CLAHALT SD1FLT2.COMPH SD1FLT2.COMPH_OR_COMPL SD1FLT2.COMPL INPUT8 SD1FLT3.COMPH SD1FLT3.COMPH_OR_COMPL SD1FLT3.COMPL INPUT9 SD1FLT4.COMPH SD1FLT4.COMPH_OR_COMPL INPUT10 INPUT11 INPUT12 INPUT13 INPUT14 SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 872: Gpio Output X-Bar
OUTPUTINV register. The signal will only be seen on the GPIO if the proper OUTPUTx muxing options are selected via the GpioCtrlRegs.GPxMUX and GpioCtrlRegs.GPxGMUX registers. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 873: X-Bar Flags
There is a bit allocated for each input signal in one of the XBARFLGx registers. The flag will remain set until cleared through the appropriate XBARCLRx register. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 874: Epwm And Output X-Bars Sources
Input X-BAR TRIP9 Modules INPUT7-14 TRIP10 (ePWM X-BAR only) TRIP11 TRIP12 CLAHALT CLAHALT FLT1.COMPH FLT1.COMPL X-BAR Flags (shared) SDFMx FLT4.COMPH FLT4.COMPL Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 875: X-Bar Registers
Start Address End Address InputXbarRegs INPUT_XBAR_REGS 0x0000_7900 0x0000_791F XbarRegs XBAR_REGS 0x0000_7920 0x0000_793F EpwmXbarRegs EPWM_XBAR_REGS 0x0000_7A00 0x0000_7A3F OutputXbarRegs OUTPUT_XBAR_REGS 0x0000_7A80 0x0000_7ABF SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 876: Input_Xbar_Regs Registers
Read Write Type Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 877: Input1Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 878: Input2Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 879: Input3Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 880: Input4Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 881: Input5Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 882: Input6Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 883: Input7Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 884: Input8Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 885: Input9Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 886: Input10Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 887: Input11Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 888: Input12Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 889: Input13Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 890: Input14Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 891: Input15Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 892: Input16Select Register
NOTE: SELECT value greater than the available number of GPIO pins on a device (except 0xFFFF) will cause the destination to be driven '1'. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 893: Inputselectlock Register
1: Respective register is locked. INPUT9SELECT R/WSOnce Lock bit for INPUT9SELECT Register: 0: Respective register is not locked 1: Respective register is locked. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 894 1: Respective register is locked. INPUT1SELECT R/WSOnce Lock bit for INPUT1SELECT Register: 0: Respective register is not locked 1: Respective register is locked. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 895: Xbar_Regs Registers
Code Description Read Type Read Read Write Type Write Reset or Default Value Value after reset or the default value SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 896: Xbarflg1 Register
1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 897 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 898 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 899 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 900 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 901: Xbarflg2 Register
1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 902 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 903 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 904 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 905 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 906: Xbarflg3 Register
1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 907 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 908 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 909 1: Corresponding Input was triggered 0: Corresponding Input was not triggered Note: [1] setting of this bit has priority over clear by software SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 910: Xbarflg4 Register
Reserved 15-8 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 911: Xbarclr1 Register
Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 912 Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 913 Writing 1 to a bit in this register clears the corresponding bit in the XBARFLG1 register. Writing 0 has no effect SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 914: Xbarclr2 Register
Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 915 Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 916 Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT2 register. Writing 0 has no effect Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 917: Xbarclr3 Register
Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 918 Writing 1 to a bit in this register clears the corresponding bit in the XBARILAT3 register. Writing 0 has no effect Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 919: Xbarclr4 Register
Reserved 15-8 RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved RESERVED Reserved SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 920: Epwm_Xbar_Regs Registers
Write Type Write Write WSOnce Write SOnce Set once Reset or Default Value Value after reset or the default value Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 921: Trip4Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 922 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 923 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 924: Trip4Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 925 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 926 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 927: Trip5Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 928 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 929 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 930: Trip5Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 931 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 932 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 933: Trip7Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 934 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 935 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 936: Trip7Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 937 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 938 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 939: Trip8Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 940 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 941 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 942: Trip8Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 943 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 944 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 945: Trip9Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 946 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 947 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 948: Trip9Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 949 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 950 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 951: Trip10Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 952 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 953 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 954: Trip10Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 955 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 956 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 957: Trip11Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 958 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 959 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 960: Trip11Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 961 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 962 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 963: Trip12Mux0To15Cfg Register
10 : Select .2 input for Mux10 11 : Select .3 input for Mux10 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 964 10 : Select .2 input for Mux2 11 : Select .3 input for Mux2 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 965 10 : Select .2 input for Mux0 11 : Select .3 input for Mux0 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 966: Trip12Mux16To31Cfg Register
10 : Select .2 input for Mux26 11 : Select .3 input for Mux26 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 967 10 : Select .2 input for Mux18 11 : Select .3 input for Mux18 Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 968 10 : Select .2 input for Mux16 11 : Select .3 input for Mux16 Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 969: Trip4Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP4 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 970 1: Respective output of Mux18 is enabled to drive the TRIP4 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 971 1: Respective output of Mux9 is enabled to drive the TRIP4 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 972 1: Respective output of Mux0 is enabled to drive the TRIP4 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 973: Trip5Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP5 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 974 1: Respective output of Mux18 is enabled to drive the TRIP5 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 975 1: Respective output of Mux9 is enabled to drive the TRIP5 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 976 1: Respective output of Mux0 is enabled to drive the TRIP5 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 977: Trip7Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP7 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 978 1: Respective output of Mux18 is enabled to drive the TRIP7 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 979 1: Respective output of Mux9 is enabled to drive the TRIP7 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 980 1: Respective output of Mux0 is enabled to drive the TRIP7 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 981: Trip8Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP8 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 982 1: Respective output of Mux18 is enabled to drive the TRIP8 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 983 1: Respective output of Mux9 is enabled to drive the TRIP8 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 984 1: Respective output of Mux0 is enabled to drive the TRIP8 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 985: Trip9Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP9 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 986 1: Respective output of Mux18 is enabled to drive the TRIP9 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 987 1: Respective output of Mux9 is enabled to drive the TRIP9 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 988 1: Respective output of Mux0 is enabled to drive the TRIP9 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 989: Trip10Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP10 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 990 1: Respective output of Mux18 is enabled to drive the TRIP10 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 991 1: Respective output of Mux9 is enabled to drive the TRIP10 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 992 1: Respective output of Mux0 is enabled to drive the TRIP10 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 993: Trip11Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP11 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 994 1: Respective output of Mux18 is enabled to drive the TRIP11 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 995 1: Respective output of Mux9 is enabled to drive the TRIP11 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 996 1: Respective output of Mux0 is enabled to drive the TRIP11 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 997: Trip12Muxenable Register
1: Respective output of Mux27 is enabled to drive the TRIP12 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 998 1: Respective output of Mux18 is enabled to drive the TRIP12 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 999 1: Respective output of Mux9 is enabled to drive the TRIP12 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. SPRUI33 – November 4 2015 – Revised January 2017 Crossbar (X-BAR) Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...
Page 1000 1: Respective output of Mux0 is enabled to drive the TRIP12 of EPWM-XBAR Refer to the EPWM X-BAR section of this chapter for more details. 1000 Crossbar (X-BAR) SPRUI33 – November 4 2015 – Revised January 2017 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated...

Save PDF