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3.3.3 Watchdog Control (WDTCTL) Register, offset 0x008
The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on
time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
NOTE: Because the Watchdog Timer 1 module has an independent clocking domain, its registers
must be written with a timing gap between accesses. Software must guarantee that this
delay is inserted between back-to-back writes to WDT1 registers or between a write followed
by a read to the registers. The timing for back-to-back reads from the WDT1 module has no
restrictions. The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates
that the required timing gap has elapsed. This bit is cleared on a write operation and set
once the write completes, indicating to software that another write or read may be started
safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note
that WDT0 does not have this restriction as it runs off the system clock and therefore does
not have a WRC bit.
31
30
WRC
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-4. Watchdog Control (WDTCTL) Register Field Descriptions
Bit
Field
31
WRC
30-2
Reserved
1
RESEN
0
INTEN
3.3.4 Watchdog Interrupt Clear (WDTICR) Register, offset 0x00C
The Wwatchdog interrupt clear (WDTICR) register is the interrupt clear register. A write of any value to
this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register.
Value for a read or reset is indeterminate.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-5. Watchdog Interrupt Clear (WDTICR) Register Field Descriptions
Bit
Field
31-0
WDTINTCLR
SPRUH22I – April 2012 – Revised November 2019
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Figure 3-4. Watchdog Control (WDTCTL) Register
Reserved
R-0
Value
Description
Write compatible.
0
A write access to one of the WDT1 registers is in progress.
1
A write access is not in progress, and WDT1 registers can be read or written.
Note: This bit is reserved for WDT0 and has a reset value of 0.
Reserved
Watchdog reset enable
0
Disabled
1
Enable the watchdog module reset output.
Watchdog interrupt enable
0
Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset).
1
Interrupt event enabled. Once enabled, all writes are ignored.
Figure 3-5. Watchdog Interrupt Clear (WDTICR) Register
Value
Description
Watchdog interrupt clear
Copyright © 2012–2019, Texas Instruments Incorporated
WDTINTCLR
W-0
Register Descriptions
2
1
0
RESEN
ITEN
R/W-0
R/W-0
0
329
M3 Watchdog Timers
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