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System Control Block (SCB) Register Descriptions
25.6.3 Interrupt Control and State (INTCTRL) Register, offset 0xD04
The Interrupt Control and State (INTCTRL) register provides a set-pending bit for the NMI exception, and
set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register
indicate the exception number of the exception being processed, whether there are preempted active
exceptions, the exception number of the highest priority pending exception, and whether any interrupts are
pending.
When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and
UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits.
Note: This register can only be accessed from privileged mode.
31
30
NMISET
Reserved
R/W-0
23
22
ISRPRE
ISRPEND
R-0
R-0
15
VECPEND
R-0
7
6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-40. Interrupt Control and State (INTCTRL) Register Field Descriptions
Bit
Field
31
NMISET
30-29
Reserved
28
PENDSV
27
UNPENDSV
26
PENDSTSET
1630
Cortex-M3 Peripherals
Figure 25-34. Interrupt Control and State (INTCTRL) Register
29
28
PENDSV
R-0
R/W-0
21
Reserved
R-0
12
Value
Description
NMI Set Pending
0
On a read, indicates an NMI exception is not pending. On a write, no effect
1
On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to
pending.
Because NMI is the highest-priority exception, normally the processor enters the NMI exception
handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt
handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is
reasserted while the processor is executing that handler.
Reserved
PendSV Set Pending
0
On a read, indicates a PendSV exception is not pending. On a write, no effect.
1
On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception
state to pending.
Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by
writing a 1 to the UNPENDSV bit.
PendSV Clear Pending
0
On a write, no effect.
1
On a write, removes the pending state from the PendSV exception.
SysTick Set Pending
0
On a read, indicates a SysTick exception is not pending. On a write, no effect.
1
On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception
state to pending.
This bit is cleared by writing a 1 to the PENDSTCLR bit.
Copyright © 2012–2019, Texas Instruments Incorporated
27
26
UNPENDSV
PENDSTSET
W-0
R/W-0
19
18
11
10
RETBASE
R-0
V ECACT
R-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
25
24
PENDSTCLR
Reserved
W-0
R-0
16
VECPEND
R-0
9
8
Reserved
R-0
0
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