External Signal Connections; Refresh Configuration; Epi Sdram Signal Connections - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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SDRAM Mode

17.6.1 External Signal Connections

Table 17-1
defines how EPI module signals should be connected to SDRAMs. The table applies when
using a x16 SDRAM up to 512 megabits. Any unused EPI controller signals can be used as GPIOs or
another alternate function.
EPI Signal
EPI0S0
EPI0S1
EPI0S2
EPI0S3
EPI0S4
EPI0S5
EPI0S6
EPI0S7
EPI0S8
EPI0S9
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20-EPI0S27
EPI0S28
EPI0S29
EPI0S30
EPI0S31
(1)
If 2 signals are listed, connect the EPI signal to both pins.
(2)
Only for 256/512 megabit SDRAMs.

17.6.2 Refresh Configuration

The refresh count is based on the external clock speed and the number of rows per bank as well as the
refresh period. The RFSH field represents how many external clock cycles remain before an AUTO-
REFRESH is required. The normal formula is:
RFSH = (t
/ number_rows) /ext_clock_period
Refresh_µs
A refresh period is normally 64 ms, or 64000 µs. The number of rows is normally 4096 or 8192.The
ext_clock_period is a value expressed in µsand is derived by dividing 1000 by the clock speed expressed
in MHz. So, 50 MHz is 1000/50=20 ns, or 0.02 µs. A typical SDRAM is 4096 rows per bank if the system
clock is running at 50 MHz with an EPIBAUD register value of 0:
RFSH = (64000/4096) / 0.02 = 15.625 µs /0.02 µs = 781.25
1196
External Peripheral Interface (EPI)
Table 17-1. EPI SDRAM Signal Connections
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
(2)
A12
BA0
BA1
Copyright © 2012–2019, Texas Instruments Incorporated
(1)
SDRAM Signal
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DQML
DQMH
CAS
RAS
not used
WE
CS
CKE
CLK
SPRUH22I – April 2012 – Revised November 2019
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