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Enhanced SPI Module Overview
Master SPI
Int flag
Slave SPI
Int flag
SPISOMI
from slave
SPISIMO
from master
SPICLK signal options:
CLOCK POLARITY = 0
CLOCK PHASE = 0
CLOCK POLARITY = 0
CLOCK PHASE = 1
CLOCK POLARITY = 1
CLOCK PHASE = 0
CLOCK POLARITY = 1
CLOCK PHASE = 1
SPISTE
A
Slave writes 0D0h to SPIDAT and waits for the master to shift out the data.
B
Master sets the slave SPISTE signal low (active).
C
Master writes 058h to SPIDAT, which starts the transmission procedure.
D
First byte is finished and sets the interrupt flags.
E
Slave reads 0Bh from its SPIRXBUF (right-justified).
F
Slave writes 04Ch to SPIDAT and waits for the master to shift out the data.
G
Master writes 06Ch to SPIDAT, which starts the transmission procedure.
H
Master reads 01Ah from the SPIRXBUF (right−justified).
I
Second byte is finished and sets the interrupt flags.
J
Master reads 89h and the slave reads 8Dh from their respective SPIRXBUF. After the user's software masks off the
unused bits, the master receives 09h and the slave receives 0Dh.
K
Master clears the slave SPISTE signal high (inactive).
12.1.6 SPI FIFO Description
The following steps explain the FIFO features and help with programming the SPI FIFOs:
1. Reset. At reset the SPI powers up in standard SPI mode, the FIFO function is disabled. The FIFO
registers SPIFFTX, SPIFFRX and SPIFFCT remain inactive.
2. Standard SPI. The standard SPI mode will work with SPIINT/SPIRXINT as the interrupt source.
3. Mode change. FIFO mode is enabled by setting the SPIFFENA bit to 1 in the SPIFFTX register.
SPIRST can reset the FIFO mode at any stage of its operation.
4. Active registers. All the SPI registers and SPI FIFO registers SPIFFTX, SPIFFRX, and SPIFFCT will be
active.
5. Interrupts. FIFO mode has two interrupts one for transmit FIFO, SPITXINT and one for receive FIFO,
SPIINT/SPIRXINT. SPIINT/SPIRXINT is the common interrupt for SPI FIFO receive, receive error and
receive FIFO overflow conditions. The single SPIINT for both transmit and receive sections of the
standard SPI will be disabled and this interrupt will service as SPI receive FIFO interrupt.
6. Buffers. Transmit and receive buffers are supplemented with two 4x16 FIFOs. The one-word transmit
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C28 Serial Peripheral Interface (SPI)
Figure 12-6. Five Bits per Character
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Copyright © 2012–2019, Texas Instruments Incorporated
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SPRUH22I – April 2012 – Revised November 2019
www.ti.com
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