C28X Sx Shram Configuration Register 2 (Csxsrcr2) - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Table 5-49. C28x Sx SHRAM Configuration Register 1 (CSxSRCR1) Field Descriptions (continued)
Bit Field
16 FETCHPROTS2
15-11 Reserved
10 CPUWRPROTS1
9 DMAWRPROTS1
8 FETCHPROTS1
7-3 Reserved
2 CPUWRPROTS0
1 DMAWRPROTS0
0 FETCHPROTS0
5.2.3.5

C28x Sx SHRAM Configuration Register 2 (CSxSRCR2)

Figure 5-45. C28x Sx SHRAM Configuration Register 2 (CSxSRCR2)
31
23
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUH22I – April 2012 – Revised November 2019
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Value Description
CPU Fetch Protection S2
0 C28x CPU Fetch allowed from S2 RAM block.
1 C28x CPU Fetch not allowed from S2 RAM block.
Reserved
CPU Write Protection S1
0 C28x CPU write allowed to S1 RAM block.
1 C28x CPU write not allowed to S1 RAM block.
DMA Write Protection S1
0 C28x DMA write allowed to S1 RAM block.
1 C28x DMA write not allowed to S1 RAM block.
CPU Fetch Protection S1
0 C28x CPU Fetch allowed from S1 RAM block.
1 C28x CPU Fetch not allowed from S1 RAM block.
Reserved
CPU Write Protection S0
0 C28x CPU write allowed to S0 RAM block.
1 C28x CPU write not allowed to S0 RAM block.
DMA Write Protection S0
0 C28x DMA write allowed to S0 RAM block.
1 C28x DMA write not allowed to S0 RAM block.
CPU Fetch Protection S0
0 C28x CPU Fetch allowed from S0 RAM block.
1 C28x CPU Fetch not allowed from S0 RAM block.
Reserved
R-0
Reserved
R-0
Reserved
R-0
Reserved
R-0
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RAM Control Module Registers
27 26
CPUWRPROT DMAWRPROT
S7
R/W-0
19 18
CPUWRPROT DMAWRPROT
S6
R/W-0
11 10
CPUWRPROT DMAWRPROT
S5
R/W-0
3 2
CPUWRPROT DMAWRPROT
S4
R/W-0
25 24
FETCHPROTS
S7 7
R/W-0 R/W-0
17 16
FETCHPROTS
S6 6
R/W-0 R/W-0
9 8
FETCHPROTS
S5 5
R/W-0 R/W-0
1 0
FETCHPROTS
S4 4
R/W-0 R/W-0
469
Internal Memory