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Device Boot Modes
6.3
Device Boot Modes
This section explains the boot mode(s) supported on this device. As part of the master subsystem, M-Boot
ROM reads the boot mode GPIO on startup and boots the device accordingly.
mode GPIO configuration supported.
As will be explained in this chapter, C-Boot ROM also supports different boot modes which allow it to boot
from the control subsystem peripherals or boot-to-flash or boot-to-RAM. It is up to the master subsystem
application to start these boot mode(s) in C-Boot ROM using IPC commands.
BOOT
MODE
MASTER SUBSYSTEM BOOT MODES
NO.
0
Boot from Parallel GPIO
1
Boot to Master Subsystem RAM
Boot from Master Subsystem serial peripherals
2
(UART0/SSI0/I2C0)
3
Boot from Master Subsystem CAN interface
4
Boot from Master Subsystem Ethernet interface
5
Not supported (Defaults to Boot-to-Flash)
6
Boot-to-OTP
(5)
7
Boot to Master Subsystem Flash memory
8
Not supported (Defaults to Boot-to-Flash)
(4)
Boot from Master Subsystem serial peripheral –
9
(4)
SSI0 Master
Boot from Master Subsystem serial peripheral –
10
(4)
I2C0 Master
11
Not supported (Defaults to Boot-to-Flash)
(4)
12
Not supported (Defaults to Boot-to-Flash)
(4)
13
Not supported (Defaults to Boot-to-Flash)
(4)
14
Not supported (Defaults to Boot-to-Flash)
(4)
15
Not supported (Defaults to Boot-to-Flash)
(4)
(1) Silicon revision A allows the user to change the GPIO pins used to determine the boot mode. Silicon revision 0 does not have
this option.
(2) By default, GPIO terminals are not pulled up (they are floating).
(3) On silicon revision 0, PF2_GPIO34 is a "don't care". So, the state of PF2_GPIO34 should not affect boot mode selection.
(4) Boot Modes 8–15 are not supported on silicon revision 0.
(5) Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash.
It is advised that users should not use the unsupported boot mode configuration to let the device boot-to-
flash by default, in case TI adds new peripheral boot mode(s) in subsequent revisions of Boot ROM.
6.3.1 Configuring Alternate Boot Mode Pins
NOTE: This feature is NOT available in the Sonata Rev0 silicon.
This device offers the flexibility to select alternate boot mode pins if the factory-offered default boot mode
pins are not convenient for customer design. If the user wants to change any of the four default boot mode
pins, a 32-bit OTP location (0x680824) can be programmed in the format described below. This location,
called "OTP BOOTMODE GPIO CONFIG REGISTER," is fragmented into four 8-bit fields named
bmode_pin1 (bits 0:7), bmode_pin2 (bits 8:15), Bmode_pin3 (bits 16:23), and bmode_pin4 (bits 24:31).
OTP BOOTMODE GPIO CONFIG REGISTER at 0x680824 location.
538
ROM Code and Peripheral Booting
Table 6-1. Master Subsystem Boot Mode Selection
Copyright © 2012–2019, Texas Instruments Incorporated
PF2_GPIO34
PF3_GPIO35
(Bmode_pin4)
(2)
(Bmode_pin3)
(3)
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Table 6-1
shows the boot
(1)
PG7_GPIO47
PG3_GPIO43
(Bmode_pin2)
(Bmode_pin1)
(2)
(2)
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
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(2)
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