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McBSP Registers
Table 15-86. Pin Control Register (PCR) Field Descriptions (continued)
Bit
Field
1
CLKXP
0
CLKRP
Pin
CLKX
FSX
CLKR
FSR
15.12.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE,
RCERF, RCERG, RCERH)
Each McBSP has eight receive channel enable registers of the format shown in
one enable register for each of the receive partitions: A, B, C, D, E, F, G, and H.
summary description that applies to any bit x of a receive channel enable register.
These memory-mapped registers are only used when the receiver is configured to allow individual
enabling and disabling of the channels (RMCM = 1). For more details about the way these registers are
used, see
Section
The receive channel enable registers (RCERA...RCERH) are shown in
Table
15-88.
Figure 15-78. Receive Channel Enable Registers (RCERA...RCERH)
15
14
RCE15
RCE14
R/W-0
R/W-0
7
6
RCE7
RCE6
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-88. Receive Channel Enable Registers (RCERA...RCERH) Field Descriptions
Bit
Field
15-0
RCEx
15.12.10.1 RCERs Used in the Receive Multichannel Selection Mode
For multichannel selection operation, the assignment of channels to the RCERs depends on whether 32
or 128 channels are individually selectable, as defined by the RMCME bit. For each of these two cases,
Table 15-89
shows which block of channels is assigned to each of the RCERs used. For each RCER, the
table shows which channel is assigned to each of the bits.
1140
C28 Multichannel Buffered Serial Port (McBSP)
Value
Description
Transmit clock polarity bit. CLKXP determines the polarity of CLKX as seen on the MCLKX pin.
0
Transmit data is sampled on the rising edge of CLKX.
1
Transmit data is sampled on the falling edge of CLKX.
Receive clock polarity bit. CLKRP determines the polarity of CLKR as seen on the MCLKR pin.
0
Receive data is sampled on the falling edge of MCLKR.
1
Receive data is sampled on the rising edge of MCLKR.
Table 15-87. Pin Configuration
Selected as Output When ...
CLKXM = 1
FSXM = 1
CLKRM = 1
FSRM = 1
15.12.10.1, RCERs Used in the Receive Multichannel Selection Mode.
13
12
RCE13
RCE12
R/W-0
R/W-0
5
4
RCE5
RCE4
R/W-0
R/W-0
Value
Description
Receive channel enable bit.
For receive multichannel selection mode (RMCM = 1):
0
Disable the channel that is mapped to RCEx.
1
Enable the channel that is mapped to RCEx.
Copyright © 2012–2019, Texas Instruments Incorporated
Selected as Input When ...
CLKXM = 0
FSXM = 0
CLKRM = 0
FSRM = 0
Figure 15-78
11
10
RCE11
RCE10
R/W-0
R/W-0
3
2
RCE3
RCE2
R/W-0
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Figure
15-78. There is
Table 15-88
provides a
and described in
9
8
RCE9
RCE8
R/W-0
R/W-0
1
0
RCE1
RCE0
R/W-0
R/W-0
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