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5.2.3.11 C28x Lx RAM_INIT_DONE Register 1 (CLxRINITDONE1)
Figure 5-51. C28x Lx RAM_INIT_DONE Register 1 (CLxRINITDONE1)
31
7
6
Reserved
RAMINITDONE
C3
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-56. C28x Lx RAM_INIT_DONE Register 1 (CLxRINITDONE1) Field Descriptions
Bit
Field
31-7
Reserved
6
RAMINITDONEL
C3
5
Reserved
4
RAMINITDONEC
2
3
Reserved
2
RAMINITDONEC
1
1
Reserved
0
RAMINITDONEC
0
SPRUH22I – April 2012 – Revised November 2019
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5
4
Reserved
RAMINITDONE
C2
R-0
R-0
Value
Description
Reserved
RAM Initialization Process Status when RAMINIT is Set for C3 RAM Block
0
RAM initialization is not finished for C3 RAM block.
1
RAM initialization is done for C3 RAM block. C3 RAM can be accessed by M3 CPU.
This status bit gets cleared when the RAMINIT bit is set for C3 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for C2 RAM Block
RAM initialization is not finished for C2 RAM block.
0
RAM initialization is done for C2 RAM block. C2 RAM can be accessed by M3 CPU.
1
This status bit gets cleared when the RAMINIT bit is set for C2 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for C1 RAM Block
RAM initialization is not finished for C1 RAM block.
0
RAM initialization is done for C1 RAM block. C1 RAM can be accessed by M3 CPU.
1
This status bit gets cleared when the RAMINIT bit is set for C1 RAM block.
Reserved
RAM Initialization Process Status when RAMINIT is Set for C0 RAM Block
RAM initialization is not finished for C0 RAM block.
0
RAM initialization is done for C0 RAM block. C0 RAM can be accessed by M3 CPU.
1
This status bit gets cleared when the RAMINIT bit is set for C0 RAM block.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3
2
Reserved
RAMINITDONE
C1
R-0
R-0
RAM Control Module Registers
8
1
0
Reserved
RAMINITDONE
C0
R-0
R-0
Internal Memory
477
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