Interrupt 96-127 Clear Enable (Dis3) Register, Offset 0X18C; Interrupt 96-127 Clear Enable (Dis3) Register; Interrupt 96-127 Clear Enable (Dis3) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

NVIC Register Descriptions

25.5.9 Interrupt 96-127 Clear Enable (DIS3) Register, offset 0x18C

The Interrupt 96-127 Clear Enable (DIS3) register disables interrupts. Bit 0 corresponds to Interrupt 96; bit
31 corresponds to Interrupt 127. See the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-19. Interrupt 96-127 Clear Enable (DIS3) Register Field Descriptions
Bit Field
31-0 INT
1616
Cortex-M3 Peripherals
Figure 25-13. Interrupt 96-127 Clear Enable (DIS3) Register
Value Description
Interrupt Disable
0 On a read, indicates the interrupt is disabled. On a write, no effect.
1 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the
EN2 register, disabling interrupt [n].
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INT
R/W-0
SPRUH22I – April 2012 – Revised November 2019
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