Usb Control And Status Endpoint N High Register (Usbcsrh[N]) In Otg B/Device Mode; Usb Control And Status Endpoint 0 High Register(Usbcsrh[N]) In Otg B/Device Mode Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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The USBCSRH[n] registers in OTG B/Device mode are shown in
52.
Figure 18-49. USB Control and Status Endpoint n High Register (USBCSRH[n]) in OTG B/Device
7 6
AUTOCL ISO
R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-52. USB Control and Status Endpoint 0 High Register(USBCSRH[n])
Bit Field Value
7 AUTOCL
0
1
6 ISO
0
1
5 DMAEN
0
1
4 DISNYET/PI
DERR
0
1
3 DMAMOD
0
1
0 Reserved 0
SPRUH22I – April 2012 – Revised November 2019
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5 4
DMAEN DISNYET /
PIDERR
R/W-0 R/W-0
in OTG B/Device Mode Field Descriptions
Description
Auto Clear
No effect
Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been
unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. Care must be taken when using μDMA to unload the receive FIFO
as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in
the USBRXMAXP[n] register, see
Isochronous Transfers
Enables the receive endpoint for isochronous transfers.
Enables the receive endpoint for bulk/interrupt transfers.
DMA Request Enable
Note: Three TX and three RX endpoints can be connected to the μDMA module. If this bit is set for a
particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
Disables the μDMA request for the receive endpoint.
Enables the μDMA request for the receive endpoint.
Disable NYET / PID Error
No effect
For bulk or interrupt transactions: Disables the sending of NYET handshakes. When this bit is set, all
successfully received packets are acknowledged, including at the point at which the FIFO becomes full.
For isochronous transactions: Indicates a PID error in the received packet.
DMA Request Mode
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
An interrupt is generated after every μDMA packet transfer.
An interrupt is generated only after the entire μDMA transfer is complete.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 18-49
Mode
3 2
DMAMOD
R/W-0
Section 18.2.4.
M3 Universal Serial Bus (USB) Controller
Register Descriptions
and described in Table 18-
0
Reserved
R-0
1349