System Control Registers
1.13.7.31 High-Speed Clock Prescaler (CHISPCP) Register
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-134. High-Speed Clock Prescaler (CHISPCP) Register Field Descriptions
Bit
Field
15-3
Reserved
2-0
HSPCLK
1.13.7.32 Low-Speed Clock Prescaler (CLOSPCP) Register
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-135. Low-Speed Clock Prescaler (CLOSPCP) Register Field Descriptions
Bit
Field
15-3
Reserved
2-0
LSPCLK
246
System Control and Interrupts
Figure 1-123. High-Speed Clock Prescaler (CHISPCP) Register
Reserved
R-0
Value
Description
Reserved
High-Speed Clock Prescaler
These bits configure the high-speed peripheral clock (HSPCLK) rate relative to the C28
SYSCLKOUT:
000
HSPCLK = SYSCLKOUT / 1
001
HSPCLK = SYSCLKOUT / 2
010
HSPCLK = SYSCLKOUT / 4
011
HSPCLK = SYSCLKOUT / 6
100
HSPCLK = SYSCLKOUT / 8
101
HSPCLK = SYSCLKOUT / 10
110
HSPCLK = SYSCLKOUT / 12
Figure 1-124. Low-Speed Clock Prescaler (CLOSPCP) Register
Reserved
R-0
Value
Description
Reserved
Low-Speed Clock Prescaler
These bits configure the low-speed peripheral clock (LSPCLK) rate relative to the C28
SYSCLKOUT:
000
LSPCLK = SYSCLKOUT / 1
001
LSPCLK = SYSCLKOUT / 2
010
LSPCLK = SYSCLKOUT / 4
011
LSPCLK = SYSCLKOUT / 6
100
LSPCLK = SYSCLKOUT / 8
101
LSPCLK = SYSCLKOUT / 10
110
LSPCLK = SYSCLKOUT / 12
111
LSPCLK = SYSCLKOUT / 14
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SPRUH22I – April 2012 – Revised November 2019
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0
HSPCLK
R/W-001
0
LSPCLK
R/W-010