Nack Bit Generation; Repeated Start Condition (In This Case, 7-Bit Addressing Format); Ways To Generate A Nack Bit - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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14.2.5.3 Free Data Format
In this format (see
inserted after each data byte, which can be from 1 to 8 bits, depending on the BC field of I2CMDR. No
address or data-direction bit is sent. Therefore, the transmitter and the receiver must both support the free
data format, and the direction of the data must be constant throughout the transfer.
To select the free data format, write 1 to the free data format (FDF) bit of I2CMDR. The free data format is
not supported in the digital loopback mode (DLB = 1 in I2CMDR).
14.2.5.4 Using a Repeated START Condition
At the end of each data byte, the master can drive another START condition. Using this capability, a
master can communicate with multiple slave addresses without having to give up control of the bus by
driving a STOP condition. The length of a data byte can be from 1 to 8 bits and is selected with the BC
field of I2CMDR. The repeated START condition can be used with the 7-bit addressing, 10-bit addressing,
and free data formats.
Figure 14-10. Repeated START Condition (in This Case, 7-Bit Addressing Format)
1
7
S Slave address
1
NOTE: In Figure
of I2CMDR.

14.2.6 NACK Bit Generation

When the I2C module is a receiver (master or slave), it can acknowledge or ignore bits sent by the
transmitter. To ignore any new bits, the I2C module must send a no-acknowledge (NACK) bit during the
acknowledge cycle on the bus.
send a NACK bit.
I2C Module Condition
Slave-receiver modes
Master-receiver mode AND
Repeat mode (RM = 1 in I2CMDR)
Master-receiver mode AND
Nonrepeat mode
(RM = 0 in I2CMDR)
SPRUH22I – April 2012 – Revised November 2019
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Figure 14-9), the first byte after a START condition (S) is a data byte. An ACK bit is
Figure 14-10 shows a repeated START condition in the 7-bit addressing format.
1 1 1
n
R/W ACK Data ACK
Any
number
14-10, n = the number of data bits (from 1 to 8) specified by the bit count (BC) field
Table 14-2 summarizes the various ways you can tell the I2C module to
Table 14-2. Ways to Generate a NACK Bit
NACK Bit Generation Options
• Allow an overrun condition (RSFULL = 1 in I2CSTR)
• Reset the module (IRS = 0 in I2CMDR)
• Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you
intend to receive
• Generate a STOP condition (STP = 1 in I2CMDR)
• Reset the module (IRS = 0 in I2CMDR)
• Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you
intend to receive
• If STP = 1 in I2CMDR, allow the internal data counter to count down to 0 and thus
force a STOP condition
• If STP = 0, make STP = 1 to generate a STOP condition
• Reset the module (IRS = 0 in I2CMDR). = 1 to generate a STOP condition
• Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you
intend to receive
Copyright © 2012–2019, Texas Instruments Incorporated
1 1
7
S Slave address R/W ACK
1
I2C Module Operational Details
1 1
n
Data ACK
Any number
C28 Inter-Integrated Circuit Module
1
P
1015