Eqep Interrupt Flag (Qflg) Register; Eqep Interrupt Flag (Qflg) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

eQEP Registers
Table 9-18. eQEP Interrupt Enable(QEINT) Register Field Descriptions (continued)
Bits Name
5 PCU
4 WTO
3 QDC
2 QPE
1 PCE
0 Reserved
15
Reserved
7 6
PCR PCO
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-19. eQEP Interrupt Flag (QFLG) Register Field Descriptions
Bits Name
15- Reserved
12
11 UTO
10 IEL
9 SEL
8 PCM
7 PCR
848
C28 Enhanced QEP (eQEP) Module
Value Description
0 Interrupt is disabled
1 Interrupt is enabled
Position counter underflow interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
Watchdog time out interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
Quadrature direction change interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
Quadrature phase error interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
Position counter error interrupt enable
0 Interrupt is disabled
1 Interrupt is enabled
Reserved
Figure 9-37. eQEP Interrupt Flag (QFLG) Register
12
R-0
5 4
PCU WTO
R-0 R-0
Value Description
Always write as 0
Unit time out interrupt flag
0 No interrupt generated
1 Set by eQEP unit timer period match
Index event latch interrupt flag
0 No interrupt generated
1 This bit is set after latching the QPOSCNT to QPOSILAT
Strobe event latch interrupt flag
0 No interrupt generated
1 This bit is set after latching the QPOSCNT to QPOSSLAT
eQEP compare match event interrupt flag
0 No interrupt generated
1 This bit is set on position-compare match
Position-compare ready interrupt flag
0 No interrupt generated
1 This bit is set after transferring the shadow register value to the active position compare register.
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11 10
UTO IEL
R-0 R-0
3 2
QDC PHE
R-0 R-0
SPRUH22I – April 2012 – Revised November 2019
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9 8
SEL PCM
R-0 R-0
1 0
PCE INT
R-0 R-0