Freescale Spi Frame Format (Single Transfer) With Spo=1 And Sph=0; Freescale Spi Frame Format (Continuous Transfer) With Spo=1 And Sph=0 - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Functional Description
20.3.4.4 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0
are shown in Figure 20-7
Figure 20-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
SSIClk
SSIFss
SSIRx
SSITx
Note:
Figure 20-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
In this configuration, during idle periods:
• SSIClk is forced high
• SSIFss is forced high
• The transmit data line SSITx is arbitrarily forced low
• When the SSI is configured as a master, it enables the SSIClk pad
• When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the
SSIFss master signal being driven low, causing slave data to be immediately transferred onto the SSIRx
line of the master. The master SSITx output pad is enabled.
One-half period later, valid master data is transferred to the SSITx line. Once both the master and slave
data have been set, the SSIClk master clock pin becomes low after one additional half SSIClk period,
meaning that data is captured on the falling edges and propagated on the rising edges of the SSIClk
signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed high
between each data word transfer because the slave select pin freezes the data in its serial peripheral
register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise
the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write.
On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period
after the last bit has been captured.
20.3.4.5 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in
which covers both single and continuous transfers.
1416
M3 Synchronous Serial Interface (SSI)
and Figure 20-8
MSB
MSB
Q is undefined.
SSIClk
SSIFss
SSITx/SSIRx
LSB MSB
Copyright © 2012–2019, Texas Instruments Incorporated
4 to16 bits
LSB
4 to16 bits
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
LSB Q
LSB
MSB
Figure 20-9
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