Sci Fifo Interrupt Flags And Enable Logic; Sci Interrupt Flags - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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With the 256 clock delay the SCI module can transmit data in a maximum delayed mode with the FIFO
words shifting out with a delay of 256 baud clocks between each words. The programmable delay
facilitates communication with slow SCI/UARTs with little CPU intervention.
8. FIFO status bits. Both the transmit and receive FIFOs have status bits TXFFST or RXFFST (bits 12−0)
that define the number of words available in the FIFOs at any time. The transmit FIFO reset bit
TXFIFO and receive reset bit RXFIFO reset the FIFO pointers to zero when these bits are cleared to 0.
The FIFOs resumes operation from start once these bits are set to one.
9. Programmable interrupt levels. Both transmit and receive FIFO can generate CPU interrupts. The
interrupt trigger is generated whenever the transmit FIFO status bits TXFFST (bits 12−8) match (less
than or equal to) the interrupt trigger level bits TXFFIL (bits 4−0 ). This provides a programmable
interrupt trigger for transmit and receive sections of the SCI. Default value for these trigger level bits
will be 0x11111 for receive FIFO and 0x00000 for transmit FIFO, respectively.
Figure 13-10 and Table 13-6
16x8 bit FIFO
RX FIFO 15
RX FIFO 0
RX BUF
RX
RXSHF
TXSHF
TX
TX BUF
TX FIFO 0
TX FIFO 15
(1)
FIFO Options SCI Interrupt Source
SCI without FIFO Receive error
Receive break
Data receive
Transmit empty
SCI with FIFO Receive error and
receive break
(1)
FIFO mode TXSHF is directly loaded after delay value, TXBUF is not used.
(2)
RXERR can be set by BRKDT, FE, OE, PE flags. In FIFO mode, BRKDT interrupt is only through RXERR flag
SPRUH22I – April 2012 – Revised November 2019
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explain the operation/configuration of SCI interrupts in nonFIFO/FFO mode.
Figure 13-10. SCI FIFO Interrupt Flags and Enable Logic
RXFFOVF flag
RXFFIL
RXERR flag
RXRDY/BRKDT
TXRDY flag
TXFFIL
Auto-baud
detect logic
Table 13-6. SCI Interrupt Flags
Interrupt Flags
RXERR
BRKDT
RXRDY
TXRDY
RXERR
Copyright © 2012–2019, Texas Instruments Incorporated
RXFFIENA
RXERRINTENA
RX/BKINTENA
TXINTENA
TXFFIENA
ABD bit
CDC bit
Interrupt Enables
(2)
RXERRINTENA
RX/BKINTENA
RX/BKINTENA
TXINTENA
RXERRINTENA
C28 Serial Communications Interface (SCI)
Enhanced SCI Module Overview
SCIFFENA
1
RXINT
0
SCIFFENA
0
TXINT
1
FIFO Enable Interrupt Line
SCIFFENA
0 RXINT
0 RXINT
0 RXINT
0 TXINT
1 RXINT
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