Dma Channel Useburst Set (Dmauseburstset), Offset 0X018; Dma Channel Useburst Clear (Dmauseburstclr), Offset 0X01C; Dma Channel Software Request (Dmaswreq) Register; Dma Channel Useburst Set (Dmauseburstset) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

µDMA Register Descriptions
Figure 16-15. DMA Channel Software Request (DMASWREQ) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-22. DMA Channel Software Request (DMASWREQ) Register Field Descriptions
Bit Field
31-0 SWREQ[n]

16.7.7 DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018

Each bit of the DMAUSEBURSTSET register represents the corresponding µDMA channel. Setting a bit
disables the channel's single request input from generating requests, configuring the channel to only
accept burst requests. Reading the register returns the status of USEBURST.
If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n] bit is
cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration
(burst) size, the µDMA controller automatically clears the corresponding SET[n] bit, allowing the remaining
items to transfer using single requests. In order to resume transfers using burst requests, the
corresponding bit must be set again. A bit should not be set if the corresponding peripheral does not
support the burst request model.
Refer to Section 16.3.4
Figure 16-16. DMA Channel Useburst Set (DMAUSEBURSTSET) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-23. DMA Channel Useburst Set (DMAUSEBURSTSET) Register Field Descriptions
Bit Field
31-0 SET[n]

16.7.8 DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C

Each bit of the DMAUSEBURSTCLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAUSEBURSTSET register.
Figure 16-17. DMA Channel Useburst Clear (DMAUSEBURSTCLR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1178
M3 Micro Direct Memory Access ( µDMA)
Value Description
Channel [n] Software Request
These bits generate software requests. Bit 0 corresponds to channel 0.
These bits are automatically cleared when the software request has been completed.
0 No request generated.
1 Generate a software request for the corresponding channel.
for more details about request types.
Value Description
Channel [n] Useburst Set
Bit 0 corresponds to channel 0. This bit is automatically cleared as described above. A bit can also
be manually cleared by setting the corresponding CLR[n] bit in the DMAUSEBURSTCLR register.
0 μDMA channel [n] responds to single or burst requests.
1 μDMA channel [n] responds only to burst requests.
Copyright © 2012–2019, Texas Instruments Incorporated
SWREQ[n]
W
SET[n]
R/W-0
CLR[n]
W
SPRUH22I – April 2012 – Revised November 2019
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