Random Read; Sequential Read; I2C 8-Bit Data Stream - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Byte
1
2
3
4
5
6
7
8
...
...
17
18
19
20
21
22
...
...
...
...
LSB: 00h n
n+1
The I2C EEPROM protocol required by the I2C bootloader is shown in
first communication, which sets the EEPROM address pointer to 0x0000 and reads the KeyValue
(0x08AA) from it, is shown in
two bytes at a time.
SDA LINE
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Device
Address
SPRUH22I – April 2012 – Revised November 2019
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Table 6-29. I2C 8-Bit Data Stream
LSB: AA (KeyValue for memory width = 8 bits)
MSB: 08h (KeyValue for memory width = 8 bits)
LSB: I2CPSC[7:0]
reserved
LSB: I2CCLKH[7:0]
MSB: I2CCLKH[15:8]
LSB: I2CCLKL[7:0]
MSB: I2CCLKL[15:8]
...
Data for this section.
...
LSB: Reserved for future use
MSB: Reserved for future use
LSB: Upper half of entry point PC
MSB: Upper half of entry point PC[22:16] (Note: Always 0x00)
LSB: Lower half of entry point PC[15:8]
MSB: Lower half of entry point PC[7:0]
...
Data for this section.
...
Blocks of data in the format size/destination address/data as shown in the generic data stream
description.
...
Data for this section.
...
MSB: 00h - indicates the end of the source
Figure 6-26. All subsequent reads are shown in
Figure 6-26. Random Read
0 0 0 0
Address Address
Pointer, MSB Pointer, LSB
Figure 6-27. Sequential Read
SDA LINE
1 0 1 0 0 0 0 1 0
Device
Address
Copyright © 2012–2019, Texas Instruments Incorporated
Contents
Figure 6-26
1 0 1 0 0 0 0 1 0
Device DATA BYTE 1
Address
DATA BYTE n DATA BYTE n+1
ROM Code and Peripheral Booting
C-Boot ROM Description
and Figure 6-27. The
Figure 6-27 and are read
DATA BYTE 2
609