Dma State Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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Generate DMACHx
interrupt to CPU
at beginning of
transfer (if enabled)
WRAP_COUNT = WRAP_SIZE
ADDR = BEG_ADDR
SYNCERR = 1
BEG_ADDR += WRAP_STEP
ADDR = BEG_ADDR
WRAP_COUNT = WRAP_SIZE
Generate DMACHx interrupt
to CPU at end of
transfer (if enabled)
SPRUH22I – April 2012 – Revised November 2019
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Figure 11-6. DMA State Diagram
Copy all addr shadow registers
to Active Set
TRANSFER_COUNT = TRANSFER_SIZE
WRAP_COUNT = WRAP_SIZE
TRANSFERSTS = 1
Yes
CHINTMODE
== 0
?
No
SYNCE == 1 &
Yes
SYNCFLG == 1 &
WRAP_COUNT !=
WRAP_SIZE
?
No
BURST_COUNT = BURST_SIZE
BURSTSTS = 1
Clear PERINTFLG bit
Clear SYNCFLG bit
Out active SRC_ADDR
Read data
Out active DST_ADDR
HALT
here
BURST_
COUNT
== 0
?
Yes
ADDR += TRANSFER STEP
BURSTSTS = 0
Yes TRANSFER_
COUNT == 0
?
No
WRAP_
Yes
COUNT == 0
?
No
WRAP_COUNT--
TRANSFER_COUNT--
TRANSFERSTS = 0
Yes
CHINTMODE
== 1
?
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Address Pointer and Transfer Control
RUNSTS = 1
Yes Peripheral
HALT
here
Yes Peripheral
HALT
here
Write data
No
BURST_COUNT--
ADDR += BURST_STEP
Points where state
machine branches
to next channel
Yes
ONESHOT
== 1
?
RUNSTS = 0
No
No
CONTINUOUS
== 1
?
C28 Direct Memory Access (DMA) Module
No
int
?
No
int
?
No
Yes
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