Dma Channel Map Assignment (Dmachmap2) Register, Offset 0X518; Dma Channel Map Assignment (Dmachmap1) Register; Dma Channel Map Assignment (Dmachmap1) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

µDMA Register Descriptions
Figure 16-29. DMA Channel Map Assignment (DMACHMAP1) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-36. DMA Channel Map Assignment (DMACHMAP1) Register Field Descriptions
Bit Field
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0

16.7.21 DMA Channel Map Assignment (DMACHMAP2) Register, offset 0x518

Each bit of the DMACHMAP0 register controls the channel assignments for the first, second, and third
mapping.
1184
M3 Micro Direct Memory Access ( µDMA)
Value Description
0 Channel 15 First Assignment
1 Channel 15 Second Assignment
2 Channel 15 Third Assignment
3 Reserved
0 Channel 14 First Assignment
1 Channel 14 Second Assignment
2 Channel 14 Third Assignment
3 Reserved
0 Channel 13 First Assignment
1 Channel 13 Second Assignment
2 Channel 13 Third Assignment
3 Reserved
0 Channel 12 First Assignment
1 Channel 12 Second Assignment
2 Channel 12 Third Assignment
3 Reserved
0 Channel 11 First Assignment
1 Channel 11 Second Assignment
2 Channel 11 Third Assignment
3 Reserved
0 Channel 10 First Assignment
1 Channel 10 Second Assignment
2 Channel 10 Third Assignment
3 Reserved
0 Channel 9 First Assignment
1 Channel 9 Second Assignment
2 Channel 9 Third Assignment
3 Reserved
0 Channel 8 First Assignment
1 Channel 8 Second Assignment
2 Channel 8 Third Assignment
3 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
CHMAP1
R/W
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
0
Submit Documentation Feedback