Register Map - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Map

• FIFOs disabled
• No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), because the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation
described in Section
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register should be set to 10 decimal or 0xA. The
value to be loaded into the UARTFBRD register is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
• Disable the UART by clearing the UARTEN bit in the UARTCTL register.
• Write the integer portion of the BRD to the UARTIBRD register.
• Write the fractional portion of the BRD to the UARTFBRD register.
• Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060).
• Optionally, configure the µDMA channel (see the Micro Direct Memory Access (µDMA) chapter) and
enable the DMA option(s) in the UARTDMACTL register.
• Enable the UART by setting the UARTEN bit in the UARTCTL register.
21.6 Register Map
Figure 21-7 lists the UART registers and their offsets.
Note that the UART module clock must be enabled before the registers can be programmed. See the Run
Mode Clock Gating Control Register 1 (RCGC1) in the System Control and Interrupts chapter. . There
must be a delay of three system clocks after the UART module clock is enabled before any UART module
registers are accessed.
NOTE: The UART must be disabled (see the UARTEN bit in the UARTCTL register before any of
the control registers are reprogrammed. When the UART is disabled during a TX or RX
operation, the current transaction is completed prior to the UART stopping.
1460
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
21.3.2, the BRD can be calculated:
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SPRUH22I – April 2012 – Revised November 2019
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