Device Configuration Registers; Reset Control; Device Level Reset Sources; Master Subsystem Device Configuration - Texas Instruments Concerto F28M35 Series Technical Reference Manual

System Control Functional Description

1.2.2 Device Configuration Registers

Several registers provide users with configuration information for debug/identification purposes on this
device. This information provides the peripheral's features and indicates how much RAM and FLASH
memory are available on this part. Both master and control subsystems have their own device
configuration registers. The master subsystem can access the device configuration of both the master and
control subsystems, whereas the control subsystem can only access its own device configuration
registers. All device configuration registers are read-only in both systems.
1.2.2.1

Master Subsystem Device Configuration

Table 1-2 provides a description of the master subsystem device configuration.
Name
Device configuration or
capabilities registers
Shared memory configuration
register
M3 configuration register
1.2.2.2 Control Subsystem Device Configuration
The control subsystem core configuration registers are: CCNF0, CCNF1, CCNF2, CCNF3, and CCNF4.
All these registers are defined in the Device Identification and Device Configuration registers subsection in
the System Control Registers section.
1.3

Reset Control

This section describes the reset sources for the device and hardware functions during reset. How system
software should handle the reset cause and what Boot ROM does to handle the reset cause is also
discussed.
This device has two external reset pins: XRS for the digital subsystem and ARS for the analog subsystem
of the chip. It is recommended that these two pins be externally tied together with a board signal trace.
The XRS pin responds to an external reset signal and an internal power-on signal to reset the entire chip.
The XRS pin also drives the reset signal out of the chip to external circuitry when the master watchdog
timers (WDT0, WDT1) and master NMI watchdog timer (MNMIWD) expires. The XRS signal is internally
gated with other internal reset signals to drive individual resets to the master subsystem, control
subsystem, analog subsystem and the shared resources.
For all reset causes which reset the master subsystem, both the control subsystem and analog subsystem
are also reset, and are held in reset until software running on the master subsystem brings them out of
reset. The master subsystem boot ROM software, which gets executed each time the device is reset, will
bring both the control and analog subsystems out of reset by setting the respective bits in the CRESCNF
register.

1.3.1 Device Level Reset Sources

Table 1-3 shows various reset signals in this device and how it affects different hardware modules in the
device.
82
System Control and Interrupts
Table 1-2. Master Subsystem Device Configuration
Registers
DC1, DC2, DC4, DC6, DC7,
DC10
MEMCNF
MCNF
Copyright © 2012–2019, Texas Instruments Incorporated
Description
If a particular bit in these registers is set to "1" then the
associated feature or module is available in the device.
If a particular bit is set to "1" then that particular shared memory
is enabled.
Flash bank size and uCRC configuration
SPRUH22I – April 2012 – Revised November 2019
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