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Parity Check Mechanism
If this circuit is active, on occurrence of a dominant CAN bus level, the CAN will automatically start the
wake up sequence. It will clear the PDR bit in CAN Control register and also clear the PDA bit in Error
and Status register. The WakeUpPnd bit in CAN Error and Status register will be set. If Status
Interrupts are enabled, also an interrupt will be generated. Finally the Init bit in CAN control register will
be cleared.
After the Init bit has been cleared, the module waits until it detects 11 consecutive recessive bits on the
CAN_RX pin and then goes bus-active again.
NOTE: In local low power mode, the application should not clear the Init bit while PDR is set. If there
are any messages in the Message RAM configured as to be transmitted and the application
resets the init bit, these messages may be sent.In local low power mode, the application
should not clear the Init bit while PDR is set. If there are any messages in the Message RAM
configured as to be transmitted and the application resets the init bit, these messages may
be sent.
23.7 Parity Check Mechanism
The CAN provides a parity check mechanism to ensure data integrity of message RAM data. For each
word (32 bits) in Message RAM, one parity bit will be calculated.
Parity information is stored in the Message RAM on write accesses and will be checked against the stored
parity bit from Message RAM on read accesses.
The parity check functionality can be enabled or disabled by PMD bit field in CAN Control register, see
Section
23.15.1. In case of disabled parity check, the parity bits in message RAM will be left unchanged
on write access to data area and no check will be done on read access.
If parity checking is enabled, parity bits will be automatically generated and checked by the CAN. A parity
bit will be set, if the modulo-2-sum of the data bits is 1. This definition is equivalent to: The parity bit will be
set, if the number of 1 bits in the data is odd.
23.7.1 Behavior on Parity Error
On any read access to Message RAM, for example, during start of a CAN frame transmission, the parity
of the message object will be checked. If a parity error is detected, the PER bit in Error and Status register
will be set. If error interrupts are enabled, an interrupt would also be generated. In order to avoid the
transmission of invalid data over the CAN bus, the MsgVal bit of the message object will be reset.
The message object data can be read by the CPU, independently of parity errors. Thus, the application
has to ensure that the read data is valid, for example, by immediately checking the Parity Error Code
register on parity error interrupt.
23.8 Debug Mode
The module supports the usage of an external debug unit by providing functions like pausing CAN
activities and making message RAM content accessible from the debugger. Debug mode is entered
automatically when an external debugger is connected and the core is halted.
Before entering Debug mode, the circuit will either wait until a started transmission or reception will be
finished and Bus idle state is recognized, or immediately interrupt a current transmission or reception. This
is depending on bit IDS in
flag, in the CAN Control register. During debug mode, all CAN registers can be accessed. Reading
reserved bits will return '0'. Writing to reserved bits will have no effect. Also, the message RAM will be
memory mapped. This allows the external debug unit to read the message RAM. For the memory
organization, see
Section
NOTE: During debug mode, the Message RAM cannot be accessed via the IFx register sets.
1522
M3 Controller Area Network (CAN)
Section
23.15.1. Afterwards, the CAN enters Debug mode, indicated by InitDbg
23.14.3).
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUH22I – April 2012 – Revised November 2019
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