Non-Master Access Violation Flag Register (Mnmavflg); Non-Master Access Violation Flag Clear Register (Mnmavclr); Non-Master Access Violation Flag Register (Mnmavflg) Field Descriptions; Non-Master Access Violation Flag Clear Register (Mnmavclr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

RAM Control Module Registers

5.2.2.16 Non-Master Access Violation Flag Register (MNMAVFLG)

Figure 5-31. Non-Master Access Violation Flag Register (MNMAVFLG)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-36. Non-Master Access Violation Flag Register (MNMAVFLG) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH

5.2.2.17 Non-Master Access Violation Flag Clear Register (MNMAVCLR)

Figure 5-32. Non-Master Access Violation Flag Clear Register (MNMAVCLR)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-37. Non-Master Access Violation Flag Clear Register (MNMAVCLR) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
460
Internal Memory
Reserved
R-0
Value Description
Reserved
Non-Master CPU Write Access Violation Flag
0 Non-master CPU write access violation did not occur.
1 Non-master CPU write access violation has occurred. The M3 CPU tried to write into an Sx RAM
block for which C28x subsystem is the master.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR
register.
Non-Master DMA Write Access Violation Flag
0 Non-master µDMA write access violation did not occur.
1 Non-master µDMA write access violation has occurred. The M3 DMA tried to write into an Sx RAM
block for which C28x subsystem is the master. In this case, writes are ignored.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR
register.
Non-Master CPU Fetch Access Violation Flag
0 Non-master CPU fetch access violation did not occur.
1 Non-master CPU fetch access violation has occurred. The M3 CPU tried to fetch code from an Sx
RAM block for which C28x subsystem is the master.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR
register.
Reserved
R-0
Value Description
Reserved
Non-Master CPU Write Access Violation Clear
0 No effect.
1 Clears the corresponding non-master DMA write access violation flag.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
CPUWRITE
R-0
Reserved
R-0
3 2
CPUWRITE
R=0/W=1-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
16
1 0
DMAWRITE CPUFETCH
R-0 R-0
16
1 0
DMAWRITE CPUFETCH
R=0/W=1-0 R=0/W=1-0
Submit Documentation Feedback