Dma Bus Error Clear (Dmaerrclr), Offset 0X04C; Dma Channel Assignment (Dmachalt), Offset 0X500; Dma Channel Map Assignment (Dmachmap0) Register, Offset 0X510; Dma Bus Error Clear (Dmaerrclr) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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µDMA Register Descriptions

Table 16-32. DMA Channel Priority Clear (DMAPRIOCLR) Register Field Descriptions

16.7.17 DMA Bus Error Clear (DMAERRCLR), offset 0x04C

The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status is set if

the µDMA controller encountered a bus error while performing a transfer. If a bus error occurs on a

channel, that channel is automatically disabled by the µDMA controller. The other channels are

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-33. DMA Bus Error Clear (DMAERRCLR) Register Field Descriptions

Each bit of the DMACHALT register represents the corresponding µDMA channel. Setting a bit selects the

secondary channel assignment as specified in

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-34. DMA Channel Assignment (DMACHALT) Register Field Descriptions

Each bit of the DMACHMAP0 register controls the channel assignments for the first, second, and third

M3 Micro Direct Memory Access ( µDMA)

Channel [n] Priority Clear

Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that

channel [n] is using the default priority level.

Figure 16-26. DMA Bus Error Clear (DMAERRCLR) Register

µDMA Bus Error Status

This bit is cleared by writing a 1 to it.

No bus error is pending.

A bus error is pending.

Figure 16-27. DMA Channel Assignment (DMACHALT) Register

Channel [n] Assignment Select

Use the primary channel assignment.

Use the secondary channel assignment.

SPRUH22I – April 2012 – Revised November 2019

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