Dma Channel Enable Clear (Dmaenaclr), Offset 0X02C; Dma Channel Primary Alternate Set (Dmaaltset), Offset 0X030; Dma Channel Enable Set (Dmaenaset) Register; Dma Channel Enable Clear (Dmaenaclr) Register - Texas Instruments Concerto F28M35 Series Technical Reference Manual

µDMA Register Descriptions
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-27. DMA Channel Enable Set (DMAENASET) Register Field Descriptions
Bit Field
31-0 SET[n]

16.7.12 DMA Channel Enable Clear (DMAENACLR), offset 0x02C

Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit clears
the corresponding SET[n] bit in the DMAENASET register.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-28. DMA Channel Enable Clear (DMAENACLR) Register Field Descriptions
Bit Field
31-0 CLR[n]

16.7.13 DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030

Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to use the alternate control data structure. Reading the register returns the
status of which control data structure is in use for the corresponding µDMA channel.
Figure 16-22. DMA Channel Primary Alternate Set (DMAALTSET) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-29. DMA Channel Primary Alternate Set (DMAALTSET) Register Field Descriptions
Bit Field
31-0 SET[n]
1180
M3 Micro Direct Memory Access ( µDMA)
Figure 16-20. DMA Channel Enable Set (DMAENASET) Register
Value Description
Channel [n] Enable Set
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAENACLR register.
0 μDMA Channel [n] is disabled.
1 μDMA Channel [n] is enabled.
Figure 16-21. DMA Channel Enable Clear (DMAENACLR) Register
Value Description
Clear Channel [n] Enable Clear
Note: The controller disables a channel when it completes the µDMA cycle.
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel
[n] is disabled for μDMA transfers.
Value Description
Channel [n] Alternate Set
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAALTCLR register.
Note: For Ping-Pong and Scatter-Gather cycle types, the µDMA controller automatically sets these
bits to select the alternate channel control data structure.
0 μDMA channel [n] is using the primary control structure.
1 μDMA channel [n] is using the alternate control structure.
Copyright © 2012–2019, Texas Instruments Incorporated
SET[n]
R/W-0
CLR[n]
W
SET[n]
R/W-0
SPRUH22I – April 2012 – Revised November 2019
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