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Peripheral
EPI WFIFO
EPI NBRFIFO
Ethernet TX
Ethernet RX
General-Purpose Timer
SSI TX
SSI RX
UART TX
UART RX
USB TX
USB RX
16.3.4.1 Single Request
When a single request is detected, and not a burst request, the µDMA controller transfers one item and
then stops to wait for another request.
16.3.4.2 Burst Request
When a burst request is detected, the µDMA controller transfers the number of items that is the lesser of
the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration size should
be the same as the number of data items that the peripheral can accommodate when making a burst
request. For example, the UART generates a burst request based on the FIFO trigger level. In this case,
the arbitration size should be set to the amount of data that the FIFO can transfer when the trigger level is
reached. A burst transfer runs to completion once it is started, and cannot be interrupted, even by a higher
priority channel. Burst transfers complete in a shorter time than the same number of non-burst transfers.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps the
nature of the data is such that it only makes sense when transferred together as a single unit rather than
one piece at a time. The single request can be disabled by using the DMA Channel Useburst Set
(DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the µDMA controller only
responds to burst requests for that channel.
16.3.5 Channel Configuration
The µDMA controller uses an area of system memory to store a set of channel control structures in a
table. The control table may have one or two entries for each µDMA channel. Each entry in the table
structure contains source and destination pointers, transfer size, and transfer mode. The control table can
be located anywhere in system memory, but it must be contiguous and aligned on a 1024-byte boundary.
Table 16-3
shows the layout in memory of the channel control table. Each channel may have one or two
control structures in the control table: a primary control structure and an optional alternate control
structure. The table is organized so that all of the primary entries are in the first half of the table, and all
the alternate structures are in the second half of the table. The primary entry is used for simple transfer
modes where transfers can be reconfigured and restarted after each transfer is complete. In this case, the
alternate control structures are not used and therefore only the first half of the table must be allocated in
memory; the second half of the control table is not necessary, and that memory can be used for
something else. If a more complex transfer mode is used such as ping-pong or scatter-gather, then the
alternate control structure is also used and memory space should be allocated for the entire table.
Any unused memory in the control table may be used by the application. This includes the control
structures for any channels that are unused by the application as well as the unused control word for each
channel.
SPRUH22I – April 2012 – Revised November 2019
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Table 16-2. Request Type Support
Single Request Signal
None
None
TX FIFO empty
RX packet received
Raw interrupt pulse
TX FIFO Not Full
RX FIFO Not Empty
TX FIFO Not Full
RX FIFO Not Empty
None
None
Copyright © 2012–2019, Texas Instruments Incorporated
Functional Description
Burst Request Signal
WFIFO Level (configurable)
NBRFIFO Level (configurable)
None
None
None
TX FIFO Level (fixed at 4)
RX FIFO Level (fixed at 4)
TX FIFO Level (configurable)
RX FIFO Level (configurable)
FIFO TXRDY
FIFO RXRDY
M3 Micro Direct Memory Access ( µDMA)
1153
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