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In this configuration, during idle periods:
•
SSIClk is forced low
•
SSIFss is forced high
•
The transmit data line SSITx is arbitrarily forced low
•
When the SSI is configured as a master, it enables the SSIClk pad
•
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the
SSIFss master signal being driven low, causing slave data to be enabled onto the SSIRx input line of the
master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Once both the master and
slave data have been set, the SSIClk master clock pin goes high after one additional half SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss
line is returned to its idle high state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed high
between each data word transfer because the slave select pin freezes the data in its serial peripheral
register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise
the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write.
On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period
after the last bit has been captured.
20.3.4.3 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in the figure
below, in which covers both single and continuous transfers.
Figure 20-6. Freescale SPI Frame Format with SPO =0 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Note: Q is undefined
In this configuration, during idle periods:
•
SSIClk is forced low
•
SSIFss is forced high
•
The transmit data line SSITx is arbitrarily forced low
•
When the SSI is configured as a master, it enables the SSIClk pad
•
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the
SSIFss master signal being driven low. The master SSITx output is then enabled. After an additional one-
half SSIClk period, both master and slave valid data are enabled onto their respective transmission lines.
At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling
edges and propagated on the rising edges of the SSIClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its
idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held low between successive data words, and
termination is the same as that of the single word transfer.
SPRUH22I – April 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
4 to16 bits
M3 Synchronous Serial Interface (SSI)
Functional Description
LSB
Q
LSB
1415
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