I2C Status Register (I2Cstr); I2C Status Register (I2Cstr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

I2C Module Registers
15 14
Reserved SDIR
R-0 R/W1C-0
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing 0 has no effect); R = Read only; -n = value after reset
Bit Field
15 Reserved
14 SDIR
13 NACKSNT
12 BB
11 RSFULL
10 XSMT
9 AAS
1026
C28 Inter-Integrated Circuit Module
Figure 14-19. I2C Status Register (I2CSTR)
13 12
NACKSNT BB
R/W1C-0 R-0
5 4
SCD XRDY
R/W1C-0 R-1
Table 14-10. I2C Status Register (I2CSTR) Field Descriptions
Value Description
0 This reserved bit location is always read as zeros. A value written to this bit has no effect.
Slave direction bit
0 I2C is not addressed as a slave transmitter. SDIR is cleared by one of the following events:
• It is manually cleared. To clear this bit, write a 1 to it.
• Digital loopback mode is enabled.
• A START or STOP condition occurs on the I2C bus.
1 I2C is addressed as a slave transmitter.
NACK sent bit. This bit is used when the I2C module is in the receiver mode. One instance in which
NACKSNT is affected is when the NACK mode is used (see the description for NACKMOD in
Section 14.5.1).
0 NACK not sent. NACKSNT bit is cleared by any one of the following events:
• It is manually cleared. To clear this bit, write a 1 to it.
• The I2C module is reset (either when 0 is written to the IRS bit of I2CMDR or when the whole
device is reset).
1 NACK sent: A no-acknowledge bit was sent during the acknowledge cycle on the I2C-bus.
Bus busy bit. BB indicates whether the I2C-bus is busy or is free for another data transfer. See the
paragraph following the table for more information.
0 Bus free. BB is cleared by any one of the following events:
• The I2C module receives or transmits a STOP bit (bus free).
• The I2C module is reset.
1 Bus busy: The I2C module has received or transmitted a START bit on the bus.
Receive shift register full bit. RSFULL indicates an overrun condition during reception. Overrun
occurs when new data is received into the shift register (I2CRSR) and the old data has not been
read from the receive register (I2CDRR). As new bits arrive from the SDA pin, they overwrite the
bits in I2CRSR. The new data will not be copied to ICDRR until the previous data is read.
0 No overrun detected. RSFULL is cleared by any one of the following events:
• I2CDRR is read is read by the CPU. Emulator reads of the I2CDRR do not affect this bit.
• The I2C module is reset.
1 Overrun detected
Transmit shift register empty bit. XSMT = 0 indicates that the transmitter has experienced
underflow. Underflow occurs when the transmit shift register (I2CXSR) is empty but the data
transmit register (I2CDXR) has not been loaded since the last I2CDXR-to-I2CXSR transfer. The
next I2CDXR-to-I2CXSR transfer will not occur until new data is in I2CDXR. If new data is not
transferred in time, the previous data may be re-transmitted on the SDA pin.
0 Underflow detected (empty)
1 No underflow detected (not empty). XSMT is set by one of the following events:
• Data is written to I2CDXR.
• The I2C module is reset
Addressed-as-slave bit
0 In the 7-bit addressing mode, the AAS bit is cleared when receiving a NACK, a STOP condition, or
a repeated START condition. In the 10-bit addressing mode, the AAS bit is cleared when receiving
a NACK, a STOP condition, or by a slave address different from the I2C peripheral's own slave
address.
1 The I2C module has recognized its own slave address or an address of all zeros (general call).
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
RSFULL XSMT
R-0 R-1
3 2
RRDY ARDY
R/W1C-0 R/W1C-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
9 8
AAS AD0
R-0 R-0
1 0
NACK AL
R/W1C-0 R/W1C-0
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