Ssi_Regs Registers; Ssi_Regs Access Type Codes - Texas Instruments Concerto F28M35 Series Technical Reference Manual

SSI Registers

20.5.2 SSI_REGS Registers

Table 20-2 lists the SSI_REGS registers. All register offset addresses not listed in
considered as reserved locations and the register contents should not be modified.
Offset Acronym
0h SSICR0
4h SSICR1
8h SSIDR
Ch SSISR
10h SSICPSR
14h SSIIM
18h SSIRIS
1Ch SSIMIS
20h SSIICR
24h SSIDMACTL
FB0h SSIPV
FC0h SSIPP
FC4h SSIPC
FD0h SSIPeriphID4
FD4h SSIPeriphID5
FD8h SSIPeriphID6
FDCh SSIPeriphID7
FE0h SSIPeriphID0
FE4h SSIPeriphID1
FE8h SSIPeriphID2
FECh SSIPeriphID3
FF0h SSIPCellID0
FF4h SSIPCellID1
FF8h SSIPCellID2
FFCh SSIPCellID3
Complex bit access types are encoded to fit into small table cells.
used for access types in this section.
1420
M3 Synchronous Serial Interface (SSI)
Table 20-2. SSI_REGS Registers
Register Name
SSI Control 0
SSI Control 1
SSI Data
SSI Status
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
SSI Masked Interrupt Status
SSI Interrupt Clear
SSI DMA Control
SSI Peripheral Version
SSI Peripheral Properties
SSI Peripheral Configuration
SSI Peripheral Identification 4
SSI Peripheral Identification 5
SSI Peripheral Identification 6
SSI Peripheral Identification 7
SSI Peripheral Identification 0
SSI Peripheral Identification 1
SSI Peripheral Identification 2
SSI Peripheral Identification 3
SSI PrimeCell Identification 0
SSI PrimeCell Identification 1
SSI PrimeCell Identification 2
SSI PrimeCell Identification 3
Table 20-3. SSI_REGS Access Type Codes
Access Type Code
Read Type
R R
R-0 R
-0
Write Type
W W
W1S W
1S
Reset or Default Value
-n
Register Array Variables
Copyright © 2012–2019, Texas Instruments Incorporated
Write Protection
Table 20-3
Description
Read
Read
Returns 0s
Write
Write
1 to set
Value after reset or the default
value
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
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