Cpu Id Base (Cpuid) Register, Offset 0Xd00; Cpu Id Base (Cpuid) Register; Cpu Id Base (Cpuid) Register Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

www.ti.com

25.6.2 CPU ID Base (CPUID) Register, offset 0xD00

The CPU ID Base (CPUID) register contains the ARMA
and implementation information.
Note: This register can only be accessed from privileged mode.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-24 IMP
23-20 VAR
19-16 CON
15-4 PARTNO
3-0 REV
SPRUH22I – April 2012 – Revised November 2019
Submit Documentation Feedback
Figure 25-33. CPU ID Base (CPUID) Register
IMP
R-0
PARTNO
R-0
Table 25-39. CPU ID Base (CPUID) Register Field Descriptions
Value Description
Implementer Code
41h ARM
Variant NumARMber
2h The rn value in the rnpn product revision identifier, for example, the 2 in r2p0.
Constant
Fh Always reads as 0xF.
Part Number
0xC23 Cortex-M3 processor.
Revision Number
0h The pn value in the rnpn product revision identifier, for example, the 0 in r2p0
Copyright © 2012–2019, Texas Instruments Incorporated
System Control Block (SCB) Register Descriptions
Cortex™-M3 processor part number, version,
®
24 23
VAR
R-0
20 19
CON
R-0
4 3
REV
R-0
Cortex-M3 Peripherals
16
0
1629