Gpio34, Gpio135 Multiplexing Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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C28 General-Purpose Input/Output (GPIO)
GPIOLPMSE2
0 = PU disabled (reset value)
1 = PU enabled
PU
GPIOPUR
GPIOx
High
impedance
output
control
XRS
A
GPxDAT latch/read are accessed at the same memory location.
B
Pull-up selection is only controlled by the M3 GPIO registers except GPIO128-GPIO135, which is controlled by the
GPEPUD register.
C
GPIO32 - GPIO63 only.
Notes:
Note the bit polarity difference between GPIOPUR and GPEPUD registers when enabling pullups.
Open drain selection is only controlled by the M3 GPIO registers
The appropriate bits in the GPIOCSEL registers (M3 GPIO registers) must be set to use the C28
GPIOs. If the GPIO is set as an M3 GPIO, the C28 GPIO MUX inputs are still active and can be read.
The input qualification circuit is not reset when modes are changed (such as changing from output to
372
General-Purpose Input/Output (GPIO)
Figure 4-37. GPIO34, GPIO135 Multiplexing Diagram
(C)
LPMCR0
Low power
modes block
GPIOx.async
SYSCLKOUT
(B)
Sync
Qual
async
GPxCTRL
GPxQSEL 1/2
GPxMUX 1/2
0 = input, 1 = output
Copyright © 2012–2019, Texas Instruments Incorporated
(default
on reset)
00
00
3 samples
01
01
6 samples
10
10
11
11
2
(default on reset)
00
01
10
11
2
00
01
10
11
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
GPxDAT (read)
N/C
(default on reset)
Peripheral 1 input
Peripheral 2 input
Peripheral 3 input
GPxSET,
GPxCLEAR,
GPxTOGGLE
GPIOx_OUT
(A)
GPxDAT
(latch)
Peripheral 1 output
Peripheral 2 output
Peripheral 3 output
(default on reset)
GPIOx _ DIR
GPxDIR
(latch)
Peripheral 1 output enable
Peripheral 2 output enable
Peripheral 3 output enable
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