Analog Subsystem Block Diagram - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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10.1 Overview
The analog subsystem consists of dual 12-bit ADC modules and six comparators with six internal 10-bit
DACs. Each ADC module block has two sample and hold circuits and three comparators plus three
internal 10-bit DACs.
The analog subsystem is accessed by the analog common interface bus (ACIB). The ACIB is responsible
for transferring triggers initiated by the control subsystem to the analog subsystem and transferring
interrupts initiated by the analog subsystem to both the master subsystem and control subsystem. The
ACIB also transfers analog register read and write data and ADC conversion results.
Figure 10-1
shows the block diagram of the analog subsystem.
ADC1INA0
ADC1INA1
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA5
ADC1INA6
ADC1INA7
ADC1INB0
ADC1INB1
ADC1INB2
ADC1INB3
ADC1INB4
ADC1INB5
ADC1INB6
ADC1INB7
ADC2INA0
ADC2INA1
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA5
ADC2INA6
ADC2INA7
ADC2INB0
ADC2INB1
ADC2INB2
ADC2INB3
ADC2INB4
ADC2INB5
ADC2INB6
ADC2INB7
Notice in the figure that ADC2 channel A1 is internally connected to ADC1 channel A0, and ADC1 channel
A1 is internally connected to ADC2 channel A0. ADC2 channel B1 is internally connected to ADC1
channel B0, and ADC1 channel B1 is internally connected to ADC2 channel B0.
10.2 Analog Common Interface Bus (ACIB)
The ACIB handles all interaction between the analog subsystem and the digital subsystem (where digital
subsystem includes the master and control subsystems). A simplified model of the ACIB is shown in
Figure 10-2
and the signals are defined in
SPRUH22I – April 2012 – Revised November 2019
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Figure 10-1. Analog Subsystem Block Diagram
ADC1
Sample
Hold
Circuit
COMP1
COMP2
Sample
Hold
Circuit
COMP3
ADC2
Sample
Hold
Circuit
COMP4
COMP5
Sample
Hold
Circuit
COMP6
Table
10-1.
Copyright © 2012–2019, Texas Instruments Incorporated
Master Subsystem
Analog
Common
Interface
Bus
Control Subsystem
Analog Subsystem
Overview
855

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