Sci Communication Control Register (Sciccr); Sci Communication Control Register (Sciccr) - Address 7050H; Sci Communication Control Register (Sciccr) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

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13.3.2 SCI Communication Control Register (SCICCR)

SCICCR defines the character format, protocol, and communications mode used by the SCI.
Figure 13-12. SCI Communication Control Register (SCICCR) — Address 7050h
7 6
STOP BITS EVEN/ODD
PARITY
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-9. SCI Communication Control Register (SCICCR) Field Descriptions
Bit Field
7 STOP BITS
6 EVEN/ODD PARITY
5 PARITY ENABLE
4 LOOP BACK ENA
3 ADDR/IDLE MODE
2-0 SCI CHAR2−0
SPRUH22I – April 2012 – Revised November 2019
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5 4
PARITY LOOPBACK
ENABLE ENA
R/W-0 R/W-0
Value Description
SCI number of stop bits. This bit specifies the number of stop bits transmitted. The receiver
checks for only one stop bit.
0 One stop bit
1 Two stop bits
SCI parity odd/even selection. If the PARITY ENABLE bit (SCICCR, bit 5) is set, PARITY (bit
6) designates odd or even parity (odd or even number of bits with the value of 1 in both
transmitted and received characters).
0 Odd parity
1 Even parity
SCI parity enable. This bit enables or disables the parity function. If the SCI is in the address-
bit multiprocessor mode (set using bit 3 of this register), the address bit is included in the
parity calculation (if parity is enabled). For characters of less than eight bits, the remaining
unused bits should be masked out of the parity calculation.
0 Parity disabled; no parity bit is generated during transmission or is expected during reception
1 Parity is enabled
Loop Back test mode enable. This bit enables the Loop Back test mode where the Tx pin is
internally connected to the Rx pin.
0 Loop Back test mode disabled
1 Loop Back test mode enabled
SCI multiprocessor mode control bit. This bit selects one of the multiprocessor protocols.
Multiprocessor communication is different from the other communication modes because it
uses SLEEP and TXWAKE functions (bits SCICTL1, bit 2 and SCICTL1, bit 3, respectively).
The idle-line mode is usually used for normal communications because the address-bit mode
adds an extra bit to the frame. The idle-line mode does not add this extra bit and is compatible
with RS-232 type communications.
0 Idle-line mode protocol selected
1 Address-bit mode protocol selected
Character-length control bits 2−0. These bits select the SCI character length from one to eight
bits. Characters of less than eight bits are right-justified in SCIRXBUF and SCIRXEMU and
are padded with leading zeros in SCIRXBUF. SCITXBUF doesn't need to be padded with
leading zeros. The bit values and character lengths for SCI CHAR2-0 bits are as follows:
SCI CHAR2
0
0
0
0
1
1
1
1
Copyright © 2012–2019, Texas Instruments Incorporated
3 2
ADDR/IDLE SCICHAR2
MODE
R/W-0 R/W-0
SCI CHAR2−0 Bit Values (Binary)
SCI CHAR1 SCI CHAR0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
C28 Serial Communications Interface (SCI)
SCI Registers
1 0
SCICHAR1 SCICHAR0
R/W-0 R/W-0
Character
Length (Bits)
1
2
3
4
5
6
7
8
995