Usb Fifo Endpoint N Register (Usbfifo[0]-Usbfifo[15]); Usb Fifo Endpoint N Register (Usbfifo[N]); Usb Fifo Endpoint N Register (Usbfifo[N]) Field Descriptions - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Register Descriptions

18.5.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15])

NOTE: Use caution when reading these registers. Performing a read may change bit status.
The USB FIFO endpoint n 32-bit registers (USBFIFO[n]) provide an address for CPU access to the FIFOs
for each endpoint. Writing to these addresses loads data into the Transmit FIFO for the corresponding
endpoint. Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
Transfers to and from FIFOs can be 8-bit, 16-bit or 32-bit as required, and any combination of accesses is
allowed provided the data accessed is contiguous. All transfers associated with one packet must be of the
same width so that the data is consistently byte-, halfword- or word-aligned. However, the last transfer
may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word
transfer.
Depending on the size of the FIFO and the expected maximum packet size, the FIFOs support either
single-packet or double-packet buffering (see Single-Packet Buffering in
of multiple packets is not supported as flags must be set after each packet is written.
Following a STALL response or a transmit error on endpoint 1–15, the associated FIFO is completely
flushed.
For the specific offset for each FIFO register see
Mode(s): OTG A or Host
USBFIFO0-15 are shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-20. USB FIFO Endpoint n Register (USBFIFO[n]) Field Descriptions
Bit Field
31-0 EPDATA 0x0000.0000
1318
M3 Universal Serial Bus (USB) Controller
OTG B or Device
Figure 18-17 and described in
Figure 18-17. USB FIFO Endpoint n Register (USBFIFO[n])
Reset Description
Endpoint Data. Writing to this register loads the data into the Transmit FIFO and reading
unloads data from the Receive FIFO.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-4.
Table 18-20.
EPDATA
R/W-0
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Section 18.2.1.1.2). Burst writing
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