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General-Purpose Input/Output (GPIO)
Port
Commit
Control
Control
GPIOPCTL
GPIOLOCK
GPIOAPSEL
GPIOCR
Periph 0
Periph 1
Alternate OutputEnable
Periph n
Data
Control
GPIODATA
GPIODIR
Interrupt
Control
GPIOIS
Interrupt
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
4.1.3.1
Master Control
The M3 GPIO mux is the master, and at boot time, the user needs to allocate which core (M3 or C28)
controls which pin. By default, all pins are assigned to the M3 GPIO mux except Group 2 GPIOs. See
Section 4.2
for more information.
To select which core controls a GPIO pin, use the GPIO Core Select (GPIOCSEL) register. If the M3
GPIOs are enabled by the GPIODEN register, the M3 can still monitor any GPIO, even if it is mapped to
the C28 GPIO mux.
4.1.3.2
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
4.1.3.2.1 Data Direction Operation
The GPIO Direction (GPIODIR) register is used to configure each individual pin as an input or output.
When the data direction bit is cleared, the GPIO is configured as an input, and the corresponding data
register bit captures and stores the value on the GPIO port. When the data direction bit is set, the GPIO is
configured as an output, and the corresponding data register bit is driven out on the GPIO port.
342
General-Purpose Input/Output (GPIO)
Figure 4-1. Digital I/O Pads
Mode
Control
GPIOAFSEL
Alternate Input
Alternate Output
GPIO Input
GPIO Output
GPIO OutputEnable
Pad
Control
GPIOPUR
GPIOODR
GPIODEN
GPIOAMSEL
GPIOCSEL
Identification Registers
GPIOPeriphID4
GPIOPCellID0
GPIOPeriphID5
GPIOPCellID1
GPIOPeriphID6
GPIOPCellID2
GPIOPeriphID7
GPIOPCellID3
Copyright © 2012–2019, Texas Instruments Incorporated
Pad Input
Digital
Pad Output
I/O
Pad
Pad Output
Enable
SPRUH22I – April 2012 – Revised November 2019
www.ti.com
Package I/OPin
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