Set The Receive Clock Mode; Frame Of Period 16 Clkg Periods And Active Width Of 2 Clkg Periods; Register Bits Used To Set The Receive Clock Mode - Texas Instruments Concerto F28M35 Series Technical Reference Manual

Receiver Configuration
Table 15-39. Register Bits Used to Set the SRG Frame-Synchronization Period and Pulse
Register Bit
Figure 15-49. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
1
CLKG
FSG
When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1
and FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted
down on every CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame
period value (FPER + 1) is also counting down. When this value reaches 0, FSG goes high, indicating a
new frame.

15.8.17 Set the Receive Clock Mode

Table 15-40 shows the settings for bits used to set receive clock mode.
Register Bit
PCR 8
SPCR1 15
1092
C28 Multichannel Buffered Serial Port (McBSP)
Width (continued)
Name Function
Range for (FWID + 1):
1 to 256 CLKG cycles
2 3 4 5 6 7
Frame-synchronization period: (FPER+1) x CLKG
Frame-synchronization pulse width: (FWID + 1) x CLKG
Table 15-40. Register Bits Used to Set the Receive Clock Mode
Name Function
CLKRM Receive clock mode
Case 1: Digital loopback mode not set (DLB = 0) in SPCR1.
CLKRM = 0
CLKRM = 1
Case 2: Digital loopback mode set (DLB = 1) in SPCR1.
CLKRM = 0
CLKRM = 1
DLB Digital loopback mode
DLB = 0
DLB = 1
Copyright © 2012–2019, Texas Instruments Incorporated
8 9 10 11 12 13
The MCLKR pin is an input pin that supplies the
internal receive clock (MCLKR).
Internal MCLKR is driven by the sample rate
generator of the McBSP. The MCLKR pin is an
output pin that reflects internal MCLKR.
The MCLKR pin is in the high impedance state.
The internal receive clock (MCLKR) is driven by
the internal transmit clock (CLKX). Internal
CLKX is derived according to the CLKXM bit of
PCR.
Internal MCLKR is driven by internal CLKX. The
MCLKR pin is an output pin that reflects internal
MCLKR. Internal CLKX is derived according to
the CLKXM bit of PCR.
Digital loopback mode is disabled.
Digital loopback mode is enabled. The receive
signals, including the receive frame-
synchronization signal, are connected internally
through multiplexers to the corresponding
transmit signals.
SPRUH22I – April 2012 – Revised November 2019
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Type Reset Value
14 15 16 17 18 19
Type
R/W
R/W
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Reset
Value
0
00