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Table 15-13. Selecting a Transmit Multichannel Selection Mode With the XMCM Bits
XMCM
00b
01b
10b
11b
As an example of how the McBSP behaves in a transmit multichannel selection mode, suppose that
XMCM = 01b (all channels disabled unless individually enabled) and that you have enabled only channels
0, 15, and 39. Suppose also that the frame length is 40. The McBSP:...
1. Shifts data to the DX pin in channel 0
2. Places the DX pin in the high impedance state in channels 1-14
3. Shifts data to the DX pin in channel 15
4. Places the DX pin in the high impedance state in channels 16-38
5. Shifts data to the DX pin in channel 39
15.6.7.1 Disabling/Enabling Versus Masking/Unmasking
For transmission, a channel can be:
•
Enabled and unmasked (transmission can begin and can be completed)
•
Enabled but masked (transmission can begin but cannot be completed)
•
Disabled (transmission cannot occur)
The following definitions explain the channel control options:
Enabled channel
Masked channel
Disabled channel
Unmasked channel
15.6.7.2 Activity on McBSP Pins for Different Values of XMCM
Figure 15-35
shows the activity on the McBSP pins for the various XMCM values. In all cases, the
transmit frame is configured as follows:
•
XPHASE = 0: Single-phase frame (required for multichannel selection modes)
•
XFRLEN1 = 0000011b: 4 words per frame
SPRUH22I – April 2012 – Revised November 2019
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Transmit Multichannel Selection Mode
No transmit multichannel selection mode is on. All channels are enabled and unmasked. No channels
can be disabled or masked.
All channels are disabled unless they are selected in the appropriate transmit channel enable registers
(XCERs). If enabled, a channel in this mode is also unmasked.
The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs.
All channels are enabled, but they are masked unless they are selected in the appropriate transmit
channel enable registers (XCERs).
The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in XCERs.
This mode is used for symmetric transmission and reception.
All channels are disabled for transmission unless they are enabled for reception in the appropriate
receive channel enable registers (RCERs). Once enabled, they are masked unless they are also
selected in the appropriate transmit channel enable registers (XCERs).
The XMCME bit of MCR2 determines whether 32 channels or 128 channels are selectable in RCERs
and XCERs.
A channel that can begin transmission by passing data from the data transmit register(s)
(DXR(s)) to the transmit shift registers (XSR(s)).
A channel that cannot complete transmission. The DX pin is held in the high impedance
state; data cannot be shifted out on the DX pin.
In systems where symmetric transmit and receive provides software benefits, this feature
allows transmit channels to be disabled on a shared serial bus. A similar feature is not
needed for reception because multiple receptions cannot cause serial bus contention.
A channel that is not enabled. A disabled channel is also masked.
Because no DXR-to-XSR copy occurs, the XRDY bit of SPCR2 is not set. Therefore, no
DMA synchronization event (XEVT) is generated, and if the transmit interrupt mode
depends on XRDY (XINTM = 00b in SPCR2), no interrupt is generated.
The XEMPTY bit of SPCR2 is not affected.
A channel that is not masked. Data in the XSR(s) is shifted out on the DX pin.
Copyright © 2012–2019, Texas Instruments Incorporated
Multichannel Selection Modes
C28 Multichannel Buffered Serial Port (McBSP)
1069
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